I can't speak for any processors other than the ARM, but, for that machine, your information is essentially correct, but misleading. All programs that implement more than a couple of subroutines use a stack. What I think you mean is, risc machines (the ARM certainly) don't have dedicated stack pointer registers.

The ARM has 16 registers, of which only one has a dedicated purpose and cannot be used in any other way: R15, the program counter. All the others R0-R14 are general purpose except R14 which takes on a special meaning when a branch-with-link instruction is executed: R14 is set to the return address so that the subroutine can be exited with the instruction: Apart from that R14 can be used for any purpose along with the other fourteen.

So what about stacks? The simple answer is, you implement your own. By convention on Acorn ARM-driven machines, R13 is used as a stack pointer. You can point it anywhere you like, but it is normal to use the end of application memory space and thus implement a descending stack.

On the ARM, the multiple load/store instructions LDM and STM are used for push and pop operations. For a full, descending stack one would push with: which means: store R0, R1, R2 and R3 (four machine words) at the address pointed to by R13, decrementing its value by four (one word size) first (hence, a full stack) and further decrementing R13 by the number of bytes written minus four (so R13 has been decremented in total by the number of bytes written). Converseley, one would pop with: which means: read R0, R5, R7, R8, R9 and R10 from the address pointed to by R13, and increment R13 by the number of bytes read.

The built-in assembler simplifies this by giving four stack-related prefixes: FD, FA, ED and EA, meaning full & descending, full & ascending, empty & descending and empty & ascending respectively. These actually assemble to:and you can probably work out for yourself the corresponding STM instructions.

So, in a real program, to execute a subrouting while utilising a stack, all you have to do is:This is what I love about the ARM, and presumably RISC architectures in general. Yeah, so it doesn't specifically provide a stack. But the machine is so well-designed that you can implement one as easily as if the machine was doing it for you anyway! Flexibility and elegance - that is the impression of RISC programming I came away with.

Sorry for the length of this post, and all the ARM-specific information. I got a bit energised there!

I know u are kiddin' - but as compiler & os writer I just love to answer such questions

ofcourse functions exist - it has nothing to do with the machine; but with programming language that defines them

Sparc does have stack; so does mips too; I never used arm processor so I can say nothing about it; but generally most of todays processors are stack machines. It's just the fact that some are better designed and hide use of stack much better from application programmers then other (for example sparc do this generally very well, while pentium with limited number of registers force you to think in stack terms very early in your programms).

A word about "stack": stack is not some speciall physical device on some machines that is missing on other; it is memory area in RAM that can shrink and grove and that system uses for storing and retrieving variables. Some machine can have some register that is "programmed in factory" to be used for communitcaion with stack, while other leaves that decision to OS (or even programmer - but often is OS the one who makes that decision). So like the man said all machines that pass parameters & return values between calls are stack machines (no matter if they have speciall dedicated register or your OS dedicates one).

Like said as application programmer one don't often think about it; I don't remember which register was used for stack pointer on solaris but there is one (it's only a convention that system use and it changes a bit in different versions of solaris).

Main difference between classic risc's as sparc and mips is that you have a big number of registers avaialable compared to "cisc" (but this changes), For ex. both sparc & mips has 32 registers while pentium has in principle 8 registers (this is just an over-generalized picture; there are some float registers and some other a bit "special" registers; but let's forgett such details now). There is also some difference how those two technologies threats instructions; for example risc have a fewer fixed-lnegth instruction sets (the name comes from there) and cics has many instructions that can vary greatly in format ant execution time. Sparc programming indeed was a bit simpler since there was a few instructions that where "delayed" and they took about 2 cycles while all other took one cycle. But mips was more like pentium; many instructions where delayed and not all equal number of cycles which didn't make programming much easier then on pentium. OK cpu "stals" so you don't need to think "that" much about it ... but; it's long away from thoze buzzy words that you can read in disscussions cisc vs. risc.

by the way: there is a nice article on a subject in some old DDJ article (for those who have the ddj cd with 11 year of articles ...).

To make things faster for example sparc has something called "register window". In practice it means that your machine (at least if it comes from sun) has a much bigger nr. of registers (our has 512 registers; I think - but note sure), but only 32 are visible at time. Then you have those 32 registers divided into 4 groups by 8 registers(it's just convention). Of those 8 are global (visible all the time), 8 are local (for storing temporaries and such), 8 are input and 8 are output registers. Those windows "overleap" each other (or what's the word - sorry english is neither my first nor second language). It means that output registers of one window set are input registers to next window set. That is used for passing parameters for functions; If those registers are not enough the rest of parameters is passed on stack. There are also some system reserved registers (I really don't remember what was real picture 'coz it was about 3 years ago I did assembly on that machine). Register windows can speed up function calls (less pushing and popping to memory with calls), and also some context switches and such (u just switch pointer to new set of registers instead of pushing registers to memory). Since register number is still limited, when you run out of register sets, you push them on stack in memory. But this is used by your OS so as application programmer you don't really need to think about it (I think it's even protected-mode instruction but I'm not sure).

This is just an overwiev picture - I really don't remember all detailes. In case you get acces to real sparc computer you can always dl sparc architecture overview from suns site (it's for free) and print it out (make it 2 copies, put them in hard envelop - you r gonna need it if you are serious about it). There is also an as manual for sparc on suns site.

Mips is a bit different; It also has 32 registers but nothing like register windows or such. I have only used the simplest one (I think it was R3000; but I'm not sure), with only very simple paging and really without any OS on it. It was a lab computer done at our university. I did some interrupt programming for very simple IO (yes interrupts does exist on risc computers and there is no computer without it; and no you will not do interrupt programming unless you make an OS or at least device driver).

We developed programs actually on solaris workstations and transferred them over the serial line to the mips computer (nothing to recommend 'coz in most cases you can forgett the help of debugger and such).

Like I said before things are not really like in books; for example "old cisc's" like motorola and pentium are also implementing a lot of risc features so it's probably stupid to think about one or another. And in not-so-far feature you will probably be using itanium; which seems to be some risc like crossover: it has 128 registers and about 90-something are avialble (but 32 are visible at time); then one can define a "frame" (of those extra registers) for passing a parameters instead of pushing them to memory; actually reminds me of sparc ... but go to intel's site and check it; there is some nice reading about itanium architecture.

If you have seen around on the net that assembly on risc machines is "simpler" then assembly on cisc's; don't believe that. It doesn't matter on which machine you learn assembly programming. Bad thing is that as soon as you switch to another processor or another assembler the syntax changes and knowing one syntax doesn't really matter, because you must learn the new one. For example mips syntax has tottaly opposed order of specifying source-destination registers then sparc. Even "register offset" syntax is different ( 4(l1) opposed to [%l1+4] - or something like that if I remember).

Good thing is that assembly programming really isn't matter of knowing syntax (like programming in general isn't). It's about way of thinking. You need to come down to the wires and to think like "take this number from memory to register; now take another one, add those two numbers, save the result back to memory .... ". It's the same way of thinking both on risc or cisc .... How big number of instructions is doesn't really matter either; you alwayz have manual to look at, search for opcodes, etc ... And when you got to know one cpu, as soon as you take some advantages of it's "specialities" like for example "register windows" you can't really use them on another cpu - coz' it probaly doesn't have same "special" features.

So the point is - make it easy for yourself; download some nice assembler like nasm if you don't have it; and start coding on whatever machine you have avialable under your fingerprints. Once you got used to think in "small steps", the syntax and architecure will realy be just some details to check in a manual ... (probably some ppl wouldn't agreee - but all ppl can't feel same neither).

Or try to get new mac with G5 processoor (or even better with 2 G5 processors), or if possible some machine with itanium and forgett about mips and sparcs - they are kind a - becomming a bit dusty today.

vasudevadas and memory_leak... great posts... it's a long (10+ years) time since I thought in anything more low level than C, so reading your posts was enjoyable and informative.

nice to c I did my lessons well

thnks

I second that, Thanks for the post, memory_leak! I am just getting into assembly, I took a class at school on it, and I really enjoy it. You post was educational for me, and heps me think about what to look forward to in the future with assembly.

btw: found an old link; for thsoe interested a bit more about sparc's "register windows", a bit understandble reading is here:

http://www.sics.se/~psm/sparcstack.html

PowerPC, MIPS and Sparc all use a stack (I am talking about the calling stack not the about FP register stack here).

The main difference between a CISC and RISC is that CISC have operations (add, sub, etc.) that operates on memory locations. On RISC, it all operations are performed on register operands. x86 has always wanted to kept backward compatibility so there are a lot of hack. You need to remember that x86 has to be able to run 16-bit code (for BIOS code during bootup) and to be able to install DOS. For some obscur reason, the BIOS code was never rewritten and old instructions removed in new processors (ex: Pentium). I did some M68K (old Motorola processors - were used in old Macs and NeXT machines and maybe others). It is a CISC arch but it is cleaner than x86. If you can get your hand on one of these very old machine, it won't be expensive.


iTux

BTW, the x86 instruction set is only used as an interface to the processors nowadays. For example, AMD (I am assuming intel does a similar things) transforms all x86 instructions into RISC-like more simple instructions to be able to schedule them etc., pipeline stuff etc. i.e. for performance reasons. RISC processors problably does a similar things but simple RISC instructions are already simpler, the conversion to low-level instructions may be simpler and faster. (This last stmt is an opinion, I don't have facts about the implementation, but it kinds of make sense).

iTux

MIPs doesn't have a stack (as in dedicated stack registers and automatic program counter push/pop on sub-procedure call). You had to manage this in software.