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it is my understanding, and correct me anyone if i'm wrong...please, the makefile gives instructions to the compiler ...i.e. paths,etc. the compiler itself would be a different animal. using the makefile as a source or reference if you will.
hope that helps. good luck.
makefile (or make) does not compile, but calls the compiler or the linker.
It works in the following way:
You specify in the makefile some dependencies between files (conditions) and the command to execute. Usually this is used to check what code files have been modified and then compile only the right ones. Make only executes the commands that you specify in the makefile (being it compile or link or remove or print or anything you like)
The make utility issues the shell commands to invoke the compiler, yes. It knows what commands to issue from the makefile, which, if it is called Makefile or makefile, will be found automatically when you invoke make. If the makefile has a different name you must specify it using the -f option.