Debug a Makefile containing many Makefile scripts invocations, for a variable

BudiKusasi · 11-18-2020, 01:38 AM

How to debug a make Makefile containing many Makefile scripts invocations, to trace where a variable/identifier name is actually declared/defined with debug log of all tracked ways to finding that, when that variable is being used at RHS

rtmistler · 11-18-2020, 05:57 AM

I'd start by using the debug flag for make, -d.

pan64 · 11-18-2020, 06:53 AM

I'm afraid there is no tool which can give you direct answer to this question:

Quote:

when that variable is being used at RHS

make -p can be useful too, but anyway, makefile[s] are not shell scripts where the commands are executed line by line. The execution of any line of code may depend on the target[s] specified, the evaluation of the actual dependency tree, existence of dependent targets, environment and also the status of the commands already executed.
If you want you can insert lines like

Code:

$(info this is a message)

anywhere too, to see what's happening.

What do you want to achieve at all?

BudiKusasi · 11-19-2020, 06:07 PM

I got workaround by this 'angel of savior' command:

$(error v = $v...... )

just put variable name to find out and move this line up/down to intercept curious, suspected part, although clearly laborious it's working awesome...
at least for me

pan64 · 11-20-2020, 12:47 AM

Quote:

Originally Posted by BudiKusasi

I got workaround by this 'angel of savior' command:

$(error v = $v...... )

just put variable name to find out and move this line up/down to intercept curious, suspected part, although clearly laborious it's working awesome...
at least for me

That's what I suggested too (I think using info is a bit better than error). Anyway, if you think it is now solved please mark the thread solved.

astrogeek · 11-20-2020, 02:42 AM

You could also use the $(warning) function inside an $(if ...) instead of $(error) if you want to log some condition without terminating make, or $(info) as suggested by pan64.

You could also define an assert style macro which you could use throughout your Makefile to report and/or terminate when a variable is or is not defined.

Here is an example which tests that a variable is defined shamelessly adapted from Managing Projects With GNU Make, 3rd Edition, pages 63-80.

Code:

#First define a common assert style macro
define assert
   $(if $1,,$(error Assertion failed: $2))
endef

Then use it to define your test macro:

Code:

define assert-defined
   $(call assert,$(filter-out undefined,$(origin $1)),"$1" is undefined)
endef

Then $(assert-defined,varname) wherever you want to test that some variable is defined, and exit with error if not defined.

Your desired test appears to be the opposite case, print message if the variable is defined, so I will leave that and other adaptations as an exercise!