Debug a Makefile containing many Makefile scripts invocations, for a variable
How to debug a make Makefile containing many Makefile scripts invocations, to trace where a variable/identifier name is actually declared/defined with debug log of all tracked ways to finding that, when that variable is being used at RHS
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I'd start by using the debug flag for make, -d.
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I'm afraid there is no tool which can give you direct answer to this question:
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If you want you can insert lines like Code:
$(info this is a message) What do you want to achieve at all? |
I got workaround by this 'angel of savior' command:
$(error v = $v...... ) just put variable name to find out and move this line up/down to intercept curious, suspected part, although clearly laborious it's working awesome... at least for me |
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You could also use the $(warning) function inside an $(if ...) instead of $(error) if you want to log some condition without terminating make, or $(info) as suggested by pan64.
You could also define an assert style macro which you could use throughout your Makefile to report and/or terminate when a variable is or is not defined. Here is an example which tests that a variable is defined shamelessly adapted from Managing Projects With GNU Make, 3rd Edition, pages 63-80. Code:
#First define a common assert style macro Code:
define assert-defined Your desired test appears to be the opposite case, print message if the variable is defined, so I will leave that and other adaptations as an exercise! |
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