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well hm it doesnt look very nicely structured... but if u look closely ull notice there is a column of 0's corresponding to the CPU1 column.........
any ideas?
notice that interrupt # 0: is the only interrupt that CPU1 is serving... and by far more amounts compared to CPU0.... thats the timer as i can read.. is it reasonable that so many timer interrupts have been generated in such small time? (less than half hour)....
also what is the LOC: ? it seems to me the only 'balanced' thing between the 2 cpu's...
is it possible that CPU1 spends its time serving 0: and so - to provide balance - the kernel chooses to let CPU0 serve the other interrupts, thus leading to the many 0's in the CPU1 column????
here is an updated /proc/interrupts - taken about a quarter after the previous
Distribution: slackware64 13.37 and -current, Dragonfly BSD
Posts: 1,810
Rep:
Well this is interesting. I have a Dell Dimension E520 which has an Intel Core 2 Duo 4300 processor. Here are my findings from a Slackware 11 system with a custom 2.6.20.4 kernel:
uname -a :
Code:
bash-3.1$ uname -a
Linux dellhost 2.6.20.4 #17 SMP PREEMPT Mon May 28 03:45:43 BST 2007 i686 i686 i386 GNU/Linux
cat /proc/cpuinfo:
Code:
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Core(TM)2 CPU 4300 @ 1.80GHz
stepping : 2
cpu MHz : 1795.565
cache size : 2048 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 2
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc pni monitor ds_cpl est tm2 ssse3 cx16 xtpr lahf_lm
bogomips : 3593.14
clflush size : 64
processor : 1
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Core(TM)2 CPU 4300 @ 1.80GHz
stepping : 2
cpu MHz : 1795.565
cache size : 2048 KB
physical id : 0
siblings : 2
core id : 1
cpu cores : 2
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc pni monitor ds_cpl est tm2 ssse3 cx16 xtpr lahf_lm
bogomips : 3591.00
clflush size : 64
Distribution: Slackware 12 Kernel 2.6.24 - probably upgraded by now
Posts: 1,054
Original Poster
Rep:
Seems to me that the interrupts aren't balanced for stuff like HT etc. Only real multiple CPUs achieve any kind of balancing. Dual core systems seem to balance only the RTC interrupts.
duryodhan, I must disagree. It looks like it just depends on the dual core processor. My custom-built PC with an AMD Athlon X2 4400+ has a much more equal balancing of interrupts:
Compare my previous result where all IRQ, except LOC (by the way, what is LOC? Kernel lock?) route to CPU0. Now, I got another IRQ route to CPU1 as well.
Will look for one of my dual-core system to test out more.
By the way, according to what I read, in order to use userspace irqbalance, we need to disable the kernel's IRQ balance.
ok LOC is the local interrupt counter... it sounds like a summing indicator, but i didn't find more info on it.
as for glib2, well im on a slack11 machine (with core 2 duo 6400), so i already have package 'glib2-2.10.3-i486-1'... however this is not a development package.... or is it?
... as for glib2, well im on a slack11 machine (with core 2 duo 6400), so i already have package 'glib2-2.10.3-i486-1'... however this is not a development package.... or is it?
Ya, that is all you need.
However, for Slack 11, you need to manually edit the irqbalance's Makefile to use the running kernel's include headers. Otherwise, it won't built.
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