Quote:
Originally Posted by jefro
I am going to venture a wild guess. The actual possible size is 4 while the amount in use is 1.
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What could "possible" mean in that context.
The CPU and cache were built together in one chip. There is no way to add anything nor modify anything. The size of the L2 cache is 1MiB and the only way to get more is to discard the whole CPU chip and put in a different one, in which case no "capacity" for L2 defined by this chip would matter.
IIUC, the chip has two cores. I'm not sure how many L2 caches it has. I
think it is one 1MiB cache shared by two cores, but I'm not sure. Maybe each core has its own private 0.5MiB cache or maybe each core has its own private 1MiB cache.
If the two sizes differed by a factor of two, I might guess that the L2 caches were private so one size was per chip and one per core. But I think the L2 cache in that model is shared and the factor of four difference is not correct even if I'm wrong about the L2 cache being shared.