IRQs explained

sycamorex · 02-17-2008, 06:20 PM

Hi, I've running debian i386 on Athlon64 X2 6000+, 4GB RAM (3.2 recognised - x86 architecture). This is my /proc/interrupts

Code:

           CPU0       CPU1       
  0:         84          0   IO-APIC-edge      timer
  1:        111      36787   IO-APIC-edge      i8042
  6:          0          3   IO-APIC-edge      floppy
  7:          0          0   IO-APIC-edge      parport0
  8:          0          0   IO-APIC-edge      rtc
  9:          0          1   IO-APIC-fasteoi   acpi
 12:          0          4   IO-APIC-edge      i8042
 15:        421     124158   IO-APIC-edge      ide1
 21:      18915    7772994   IO-APIC-fasteoi   ehci_hcd:usb1, uhci_hcd:usb4, sata_via
 22:          0          0   IO-APIC-fasteoi   uhci_hcd:usb2
 23:          0          0   IO-APIC-fasteoi   uhci_hcd:usb3
 24:          0          0   IO-APIC-fasteoi   uhci_hcd:usb5
 25:      20494    7880354   IO-APIC-fasteoi   eth0
 26:       6712    3176988   IO-APIC-fasteoi   ICE1712
 27:      11407    8373929   IO-APIC-fasteoi   nvidia
NMI:          0          0 
LOC:   16740862   15132880 
ERR:          0
MIS:          0

I've got a few questions.

1. the first column shows the IRQ number. AFAIK, modern computers usually have 16 IRQs. Why is there 15 of them? Is it because IRQ 2 cascades to IRQs 8-15? Or do I have 24 IRQs (apic)? How can I check it? Why are not all the numbers used up? What I mean is why isn't it in a continuous sequence 0,1,2,3,4, etc?

2. Now a bit about the second and third columns. The second one shows the number of interrupts send from a device to the first core of my CPU since last reboot. Am I correct? If so, is there any particular reason why the second core is being more 'popular'?

3. What does the forth column mean?

4. What are those NMI, LOC, ERR, MIS

5. What are: i8042 and rtc?

thank you

Simon Bridge · 02-17-2008, 07:13 PM

Overview of IRQs.
http://en.wikipedia.org/wiki/Interrupt_request
http://www.linuxjournal.com/article/6946
Specific:
http://www.cs.cmu.edu/~ralf/files.html

Quote:

1. Why are not all the numbers used up?

Because some of them are reserved for devices that are not present.

Quote:

2. ...is there any particular reason why the second core is being more 'popular'?

Maybe, but probably not. Try another day and it may be different.

Quote:

3. What does the forth column mean?

That's the interrupt mechanism. You use intel APIC... see the specification for details. Here is a general explaination.

Quote:

5. What are: i8042 and rtc?

i8042 is the intel keyboard/mouse controller chip. rtc = real time clock.

Emerson · 02-17-2008, 07:32 PM

In addition to what Simon said, from 0 to 15 is 16.
There is a daemon called irqbalance, are you using it?

sycamorex · 02-18-2008, 03:48 PM

thanks guys, I downloaded irqbalance which seems an interesting daemon. I'll observe the balance between the two cores

Simon Bridge · 02-18-2008, 09:22 PM

Quote:

In addition to what Simon said, from 0 to 15 is 16.

That was my first thought - then I counted the actual interrupts on the list... confusing no?

Have you lot noticed that irq0-7 are sufficient for a standard 8086-based desktop machine from the 80's?

Emerson · 02-18-2008, 09:45 PM

Quote:

Have you lot noticed that irq0-7 are sufficient for a standard 8086-based desktop machine from the 80's?

I also have some vague memories about IBM machines which had negative level-triggered IRQ's which actually allowed something like IRQ sharing back then. IBM clones had positive level IRQ's causing IRQ conflicts. Or was it other way around ... hmmm ...

sycamorex · 02-19-2008, 02:34 AM

Code:

           CPU0       CPU1       
  0:         84          0   IO-APIC-edge      timer
  1:        886      14665   IO-APIC-edge      i8042
  6:          0          3   IO-APIC-edge      floppy
  7:          0          0   IO-APIC-edge      parport0
  8:          0          0   IO-APIC-edge      rtc0
  9:          0          0   IO-APIC-fasteoi   acpi
 12:          0          4   IO-APIC-edge      i8042
 15:        310      69621   IO-APIC-edge      ide1
 21:          3        678   IO-APIC-fasteoi   uhci_hcd:usb1
 22:          0          0   IO-APIC-fasteoi   uhci_hcd:usb2
 23:    1135075    1117081   IO-APIC-fasteoi   uhci_hcd:usb3, ehci_hcd:usb5, sata_via
 24:          0          0   IO-APIC-fasteoi   uhci_hcd:usb4
 25:       1180    1247523   IO-APIC-fasteoi   eth0
 26:     664831     667333   IO-APIC-fasteoi   nvidia
 27:        737    2156662   IO-APIC-fasteoi   ICE1712
NMI:          0          0 
LOC:    7582992    7913392 
ERR:          0
MIS:          0

Notice how the interrupts spread evenly on both cores (well, at least on gfx and usb-hd) after running irqbalance for 1 day.

Simon Bridge · 02-19-2008, 05:08 AM

Quote:

IBM clones had positive level IRQ's causing IRQ conflicts. Or was it other way around

I think it was the other way around... I remember the clones ended up with a rep superior to the IBM machines. I also remember IBM having the stature enjoyed by MS today

now they're the good guys: how the World turns. (We used to call them "ibbum", and the machines "chaotic-evil". By the same token, I guess MS is "Lawful-Evil".)

http://en.wikipedia.org/wiki/Intel_8...XT_and_PC.2FAT
... the legacy system we were used to.

Quote:

Notice how the interrupts spread evenly on both cores (well, at least on gfx and usb-hd) after running irqbalance for 1 day.

I was quite pleased to learn of this utility also. This is why I look to help other people here - I end up learning something I would not have thought to ask about.

Have you noticed how asking about the really low-level aspects of a computer dredges up the really old techs around here? Us "Sid" types will now go off and play Quake... with punch cards.
http://ars.userfriendly.org/cartoons/?id=20011229

onebuck · 02-19-2008, 07:23 AM

Hi,

You start loading the 'Quake' cards and call me when your through.

sycamorex · 02-20-2008, 02:30 PM

hi,
IRQs part 2

I am reading about chipsets and there is a diagram of a typical north/south bridge layout.
This is slightly confusing for me.

http://en.wikipedia.org/wiki/Southbr...28computing%29

My question is concerned with how IRQs fit in that diagram.
eg. I moved my mouse which results in an IRQ being sent from i8042 to the CPU.
My question is whether IRQ channels/paths physically exist as separate channels on
the motherboard or is the interrupt request from i8042 sent via PCI bus to the southbridge, which
via the internal bus is sent to the northbridge which finally uses FSB to send the request to the processor?

thanks

Simon Bridge · 02-20-2008, 06:35 PM

Quote:

You start loading the 'Quake' cards and call me when your through.

Done! Ahhh... no. One of the cards was out of sequence, have to redo. (Hmmm... hanging chad on this one...)

Quote:

My question is whether IRQ channels/paths physically exist as separate channels on
the motherboard

CPUs have a separate pin/s which is/are the interrupt-line/s (often: "INT REQ" on pin diagrams) It says "go look at the bus". The exact details are HW-specific. So pick a CPU and study it.

Are you thinking of scratch-building a mobo?

IRQs are too low-level to show on that diagram - which is actually pretty abstract.
Try this one:
http://tldp.org/LDP/tlk/dd/interrupts.html

The way to see how interrupts came and go, is to go to the circuit diagram - here's an old one:
http://www.z80.info/gfx/Circuit_diagram_2A_3A.gif
The CPU is the Z80 ... the IRQ line goes to the NIRQ pin (pin 20 - hunt for it). Interrupts come from the handler, which gets them from the HW interface. The PCI bus has an interrupt-line, for eg.

onebuck · 02-21-2008, 07:54 AM

Hi,

How many deck boxes? Drop any?

sycamorex · 02-22-2008, 07:35 AM

thanks Simon, it makes much more sense now.

I am thinking of putting the Z80 mobo diagram as my wallpaper

Quote:

Are you thinking of scratch-building a mobo?

Yes, mine will support 66-core CPUs, it will have 72 IRQs and 2 integrated toasters!!!

On a serious note, I started reading about a hardware side of computers, and I find
it quite interesting. It is quite weird to me not to know how computers work - I've been
using them for 18 years.

regards

sycamorex

onebuck · 02-22-2008, 09:17 AM

Hi,

The Zilog Z-80 family is still used. A great processor. Cheap and great controller chip.

markseger · 02-29-2008, 09:48 AM

having spent some time trying to monitor interrupts over time, I've added support to reporting this type of data by cpu over time with my collectl utility - see http://collectl.sourceforge.net/ but in the meanwhile to help whet your appetite, here are a couple of examples of what it will show you, in addition to lots of other types of data.

This summarizes total interrupts but cpu

# <-----------------Int----------------->
#Time Cpu0 Cpu1 Cpu2 Cpu3 Cpu4 Cpu5 Cpu6 Cpu7
12:49:55 4828 16K 1000 16K 18 16K 16K 0
12:49:56 4804 16K 1000 16K 0 16K 16K 0
12:49:57 4811 16K 1000 16K 18 16K 16K 0
12:49:58 4789 16K 1000 16K 0 17K 16K 44

and this shows the individual types of interrupts. note that since it only shows those that are actually changing, it's much easier than trying to visually parse /proc/interrupts, which is where collectl gets the data:

# INTERRUPT DETAILS
# Int Cpu0 Cpu1 Cpu2 Cpu3 Cpu4 Cpu5 Cpu6 Cpu7 Type Device(s)
12:48:50 082 0 0 0 7731 0 0 0 0 PCI-MSI-X eth2 (queue 0)
12:48:50 098 0 0 0 0 2037 0 0 0 PCI-MSI-X eth2 (queue 2)
12:48:50 122 0 0 2240 0 0 0 0 0 PCI-MSI-X eth2 (queue 5)
12:48:50 138 0 7084 0 0 0 0 0 0 PCI-MSI-X eth2 (queue 7)
12:48:50 154 0 0 0 0 0 7723 0 0 PCI-MSI-X eth3 (queue 0)
12:48:50 162 9082 0 0 0 0 0 0 0 PCI-MSI-X eth3 (queue 1)
12:48:50 178 0 0 0 0 0 0 8253 0 PCI-MSI-X eth3 (queue 3)
12:48:50 210 0 0 0 0 0 0 0 6417 PCI-MSI-X eth3 (queue 7)
12:48:50 218 1 0 0 0 0 0 0 0 PCI-MSI eth0

-mark