You should invoke gcc first on each .c file with the -c option. This means "compile to object file" - i.e. omit the linking stage. Once you have an object file for each .c file, you can link them together:
Code:
gcc -c 1.c -o 1.o
gcc -c 2.c -o 2.o
gcc -c 3.c -o 3.o
gcc 1.o 2.o 3.o -o myprogram
You can write a Makefile which includes wildcard rules like this:
Code:
%.o : %.c
gcc -c -o $@ $<
This means that all targets which end in .o will depend on a like-named file but ending in .c. In the command $@ means the target name, $< means the left most dependency name.
A simple Makefile which will generate the gcc commands above might look like this. Note that that the 8 spaces before commands should be a TAB in your Makefile - NOT spaces.
Code:
myprogram : 1.o 2.o 3.o
gcc -o myprogram 1.o 2.o 3.o
%.o : %.c
gcc -c -o $@ $<
Note that you don't need to use make at all - you can invoke all the gcc commands manually if you prefer. Make is nice because it will work out which files have been modified since the last build and re-compile and re-link only what needs to be re-compiled and re-linked. Thus as your projects become larger, make becomes more valuable, but for trivial examples like the one you describe, it's probably not worth the effort.