Here is the makefile. Is it possible to write a rule which
first search every file in same directory and then compile
and link those files which end with .cpp extension.
Requirement is that it have to pass linking rule which is in
makefile ( ie. execute @echo command during linking phase )
Dummy rule can be erased if it is required to make it work.
This is just an artificial test and there is no real world
requirements to make this work. I am just curious how to do it if
it is possible.
One last requirement. Have to be possible by single make command.
I get a working version for two make commands already.
Code:
CXXFLAGS= -ansi -Wall -pedantic
SRCS=$(wildcard *.cpp )
BINARIES=$(basename $(SRCS))
OBJS=$(subst .cpp,.o,$(SRCS))
all: $(BINARIES) $(OBJS)
%.o: %.cpp
@echo binaries are $(BINARIES) and objects are $(OBJS)
@echo mycompile $(CXX) -c $< $(CXXFLAGS)
$(CXX) -c $< $(CXXFLAGS)
%:%.o
@echo mylinking $(CXX) $< -o $@ $(LIBS)
$(CXX) $< -o $@ $(LIBS)
%:
@echo dummy rule
clean:
rm -f *.o $(BINARIES) *~ stdout.txt stderr.txt
Thank you from your time. Happy head scratching