Hi all!!
Can somebody explain me, Why there is a need for alignment restricted access in processors? I know this is the reason for buserror. I would like to know the reason for its implementation in processors.
thanks in advance
Bye,
Eshwar.

One reason is speed. Imagine the processor data bus and the RAM data bus,
32 bit, directly connected:


Bit 0 - 31

Processor Buffer0 1 2 3

Bus |||||||| |||||||| |||||||| ||||||||

Ram Byte 0 1 2 3

Now what you can see is that you have a direct connection between Processor
ReadIn buffer 0 and Ram byte 0, Proc ReadIn 1... and so on. As a lot of data
in Ram actually is 32 bit, you're fine as long as you keep it aligned modulo 4
it's adress in ram. It's also obvious that if you have some data which consists
of a char (byte) in Ram byte 0 and then a long (32bit) in byte 1-4 then the
processor will need two memory accesses to only read the long. But if you fill
in Ram byte 1-3 with padding (meaningless) bytes and therefore move your
long to byte 4-7, processor will only need one access to read the long in.

That's the basic principle - in reality hw is much more complex, and it is very
much processor dependant.

HTH

Hmmm... sorry all the spaces are cut out.... hope you can read it anyway.

Hi Thanks for your answer. I have got another doubt In the above example why its not possible to access the address 1 directly( it means just placing 1 on the address bus )? If we are able to do that one we can get 4 bytes directly on to processor buffer with single memory read. Why its not possible?
I hope you understand my question. Could you please clarify my doubt?

Well, actually you can, but since readin buffer 0 is hardwired (by thin wires
on the motherboard) to ram byte 0 (and modulo byte 4,8,12...), all you would
do is fill in readin buffers 0-3. Luckily the hw logic on the motherboard is intelligent enough to notice that you want to fill in 4 bytes from an odd adress, and does just that... by two read accesses.

Oh now i got it, thank you, thank you very much Mr. Marius.
bye,
Eshwar.