Recursive Makefile

freeindy · 06-08-2011, 10:35 AM

Hi,

I'm trying to make recursive makefile work but it's giving me two problems. I have a top folder with the main Makefile and one Makefile for each sub folder 'one' and 'two'. Makefile in subfolder 'one' and 'two' are identical.

The top Makefile (still a bit messy) looking like this:

Code:

# Directories                                                                                                  

CC = gcc
CFLAGS = -Wall -Wextra

TARGET_DIR = bin
MAIN_FILE = one.c
DIRS = one two
PATHS= $(PWD)/one:$(PWD)/two

OBJS = $(SOURCES:.c=.o)

.PHONY: all
all: $(DIRS) target

.PHONY: $(DIRS)
$(DIRS):
        $(MAKE) $(CFLAGS) --directory=$@

target: $(OBJS)
#       for d in $(DIRS); do (cd $$d; OBJS=$(wildcard *.o)); done#                                             
#       @echo $(OBJS)                                                                                          
#       $(CC) $(CFLAGS) -o bin/oas -I .                                                                        

clean:
        @echo "Cleaning up..."
        for d in $(DIRS); do (cd $$d; $(MAKE) clean); done

And makefile in each subfolder 'one' and 'two' looks like:

Code:

SRCS=$(wildcard *.c)

ifndef NDEBUG
BUILD_TYPE=debug
else
BUILD_TYPE=release
endif
#OBJS =$(addprefix $(OS_TARGET)/$(BUILD_TYPE)/, $(SRCS:.c=.o))                                                 
OBJS = $(SRCS:.c=.o)

.PHONY: all

all: os_target build place

os_target:
ifeq ($(OS_TARGET),)
        @echo "No OS target supplied... aborting."
        @exit 1
endif
        mkdir -p $(OS_TARGET)/$(BUILD_TYPE)

build: $(OBJS)
        @echo "*** Compiling $(CURDIR) for $(OS_TARGET) ***"
	$(MAKE) $(OBJS) $(CFLAGS)

place:
        mv -f *.o $(OS_TARGET)/$(BUILD_TYPE)
	@echo "*** Compiling $(CURDIR) for $(OS_TARGET) COMPLETED ***"

clean:
ifeq ($(OS_TARGET),)
	@echo "No OS target supplied... aborting."
	@exit 1
endif
     	${RM} -frv $(PWD)/$(OS_TARGET)/$(BUILD_TYPE)/*.o

First problem is that if I only have variable 'DIRS = one' then I get the following output:

Code:

make -Wall -Wextra --directory=one
make[1]: Entering directory `/home/indy/development/tmp/top/one'
mkdir -p hasse/debug
cc    -c -o one.o one.c
cc    -c -o zero.o zero.c
*** Compiling /home/indy/development/tmp/top/one for hasse ***
make one.o zero.o 
make[2]: Entering directory `/home/indy/development/tmp/top/one'
make[2]: `one.o' is up to date.
make[2]: `zero.o' is up to date.
make[2]: Leaving directory `/home/indy/development/tmp/top/one'
mv -f *.o hasse/debug
*** Compiling /home/indy/development/tmp/top/one for hasse COMPLETED ***
make[1]: Leaving directory `/home/indy/development/tmp/top/one'

It seems to try to compile twice. I don't understand why. If I change variable 'DIRS = one two'. The make goes one in infinite loop. I guess the problem is related to same error. Anyone can see why?

Thanks a million.
Indy

dwhitney67 · 06-08-2011, 01:19 PM

I cannot tell from your top-level Makefile whether you are attempting to build object files in directories 'one' and 'two', and then combine all objects files to build one executable, or if you are building two executables.

If it is the latter, then I would suggest that you keep the top-level Makefile real simple; something like:

Code:

DIRS = one two

all clean:
        @ for dir in $(DIRS); do \
                $(MAKE) -C $$dir $@; \
          done

For the Makefile in directory 'one':

Code:

APP = one

SRCS = $(wildcard *.c)
OBJS = $(SRCS:.c=.o)

DEBUG  = -g
CFLAGS = -Wall -pedantic $(DEBUG)

LDFLAGS =

.PHONY: all clean


all : $(APP)

$(APP) : $(OBJS)
        $(CC) $^ $(LDFLAGS) -o $@

clean :
        $(RM) $(OBJS)
        $(RM) $(APP)

The Makefile in directory 'two' should be quite similar to the above, with the exception being the value assigned to APP.

freeindy · 06-09-2011, 02:44 AM

Thanks dwhitney67,

Sorry for misinformation. I'm trying to build object files in all sub directories and then link them to one executable into a different folder.

The example you gave me above is the one I started from.

dwhitney67 · 06-09-2011, 04:10 AM

Quote:

Originally Posted by freeindy

I'm trying to build object files in all sub directories and then link them to one executable into a different folder.

Roger that... try the following Makefile. It will locate all of your C modules, so that it can generate the dependency and object file for each (all of which is placed in OBJDIR). If you keep header files in a separate directory (from where the .c files reside), then define the value for INCLUDE; otherwise leave it unassigned. And if you have any external library dependencies, then define LDFLAGS. Of course, adjust the value for APP. Other than that, you should not have to modify anything else.

Code:

APP      = myapp

OBJDIR   = .srcobjs

SRCS    := $(shell find . -name '*.c')
SRCDIRS := $(shell find . -name '*.c' -exec dirname {} \; | uniq)
OBJS    := $(patsubst %.c,$(OBJDIR)/%.o,$(SRCS))
DEPS    := $(patsubst %.c,$(OBJDIR)/%.d,$(SRCS))

DEBUG    = -g
INCLUDES =
CFLAGS   = $(DEBUG) -Wall -pedantic $(INCLUDES) -c
LDFLAGS  =

DEPENDS  = -MT $@ -MD -MP -MF $(subst .o,.d,$@)

SHELL    = /bin/bash

.PHONY: all clean distclean


all: buildrepo $(APP)

$(APP): $(OBJS)
	$(CC) $^ $(LDFLAGS) -o $@

$(OBJDIR)/%.o: %.c
	$(CC) $(CFLAGS) $(DEPENDS) $< -o $@

clean:
	$(RM) -r $(OBJDIR)

distclean: clean
	$(RM) $(APP)

buildrepo:
	@$(call make-repo)

define make-repo
   for dir in $(SRCDIRS); \
   do \
	mkdir -p $(OBJDIR)/$$dir; \
   done
endef

ifneq "$(MAKECMDGOALS)" "distclean"
ifneq "$(MAKECMDGOALS)" "clean"
-include $(DEPS)
endif
endif

freeindy · 06-10-2011, 10:02 AM

Thanks!

Nice solution :-). However, I have a different setting in my tree structure and the project has to compile for two different targets. But your solution gave the was. once again, thanks.

Regards
Indy