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Old 07-31-2008, 05:51 AM   #1
binarybob0001
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Registered: Dec 2004
Distribution: Debian Wheezy
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Need Help Writing a For Loop in a Makefile


Let's start with the code I have.
Code:
forms="mainform \
	colorname \
	findform \
	optionsform"

# Make a list *.ui.h file names and there respective mocced file names.
# Also create a list of file that will be generate from the *.ui files.
all:
	for i in $(forms);
	do \
		uicodefiles+=$(i).ui.h; \
		moccedfiles+=moc_$(i).cpp; \
		formcode+=$(i).h; \
		formcode+=$(i).cpp; \
	done;
	echo "Look here ********************";
	echo $(uicodefiles);
	echo $(moccedfiles);
	echo $(formcode);
When I try to use my Makefile I get
Code:
for i in "mainform colorname findform optionsform";
/bin/sh: -c: line 1: syntax error: unexpected end of file
Can anyone see what I'm doing wrong? Thanks
 
Old 07-31-2008, 06:30 AM   #2
colucix
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Try to add a backslash after the line containing for or put for and do together in the same line:
Code:
for i in $(forms); do \
 
Old 07-31-2008, 06:38 AM   #3
binarybob0001
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Registered: Dec 2004
Distribution: Debian Wheezy
Posts: 444

Original Poster
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I changed my code to this.
Code:
all:
	for i in $(forms); do \
		uicodefiles+=$(i).ui.h; \
		moccedfiles+=moc_$(i).cpp; \
		formcode+=$(i).h; \
		formcode+=$(i).cpp; \
	done; \
	echo "Look here ********************"; \
	echo $(uicodefiles); \
	echo $(moccedfiles); \
	echo $(formcode);
However the output for all three variable is
Code:
Look here ********************
You guessed it, empty. Any ideas of why this happening?
 
Old 07-31-2008, 07:51 AM   #4
ntubski
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The for loop and other commands run in a shell, they can't affect makefile variables. I think the following will do what you want:
Code:
forms := mainform colorname findform optionsform

uicodefiles := $(addsuffix .ui.h, $(forms))
moccedfiles := $(addprefix moc_, $(addsuffix .cpp, $(forms)))
formcode := $(addsuffix .cpp, $(forms)) $(addsuffix .h, $(forms))
If you do end up needing a loop, you should try the foreach function.
 
  


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