Maybe it is a hardware achitecture question, not a Linux kernel question. But I don't know where to post, so I choose here since here is the most relevent place.


I was told that the TLB orgnization is "full assocc" and cache is "directly mapped". But I think they both use some 01 bits (address) to match the content in it. What is the real difference between their orgnize?

The TLB (Translation Lookaside Buffer) is an essential part of the virtual memory system: it avoids having to look through segment- and page-tables for each memory-access.

TLB hardware works in parallel: in other words, "anyone in the room who has address $123456, please raise your hand." The virtual address is presented simultaneously to every slot.

The term "cache," per contra, can mean many things in many different contexts. It's a software construction, whereas the TLB is hardware circuitry. (And yet, it could obviously be said that "the TLB is 'a cache.'" because of the purpose that it serves.)

Yes, a cache could be many things, but I think the OP meant something like the on chip cache in, say, an Intel/AMD processor, which would be hardware.

I hope I can renmember this rubbish; I think I know where my copy of John L. Hennessy and David A. Patterson is, but I wouldn't like to get it out!

I think the OP is trying to ask about set associativity (but I could be wrong).

Assume that you are caching a memory of size (no of address bits needed to unambiguously map the address space) a. There is no point in having a cache unless the cache is a smaller memory than the area of memory being cached, otherwise you would just use the fast cache memory for everything.

Divide the address-space-to-be-cached into to two portions; the most significant n bits and the remaining bits (for an address length, a, the remaining bits will be a-n [ = m] ).

In a direct mapped or one way cache there is one location that relates to each address in the m bit address space, for a two way, there will be two, etc. What this means is that every time that you need to cache a memory adress with a least significant portion (m) of some particular value, no other memory address that has an identical m can be cached. For a two-way that can be two, etc.

So you might think that two-way (or four or eight...) would be bound to be superior. This is incorrect. (This is not a statement that a direct mapped cache is always superior.)

Firstly, a direct mapped cache is simpler to implement and the number of cycles required for access has an impact on system performance and complexity of implimentation relates to access time.

Secondly, with locality of reference the chances are high that the next addresses to be accesed will be in the vicinity if the currently accessed one and so having cache space for 'far away addresses that map over the current one, at some degree of aliasing' may be of less value than you think.