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Old 05-15-2011, 11:29 AM   #1
vijayabcdef
LQ Newbie
 
Registered: Jul 2010
Posts: 8

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chipset related problem


Hi,
I am using i815 chipset board in my PC with svgalib1.9.25 version.
vgatest in demos folder is working well without helper module in NO HELPER mode specified in /etc/vga/libvga.config
On compiling helper module and using it for vgatest, output is not correct.
I am giving output of useful commands on the target platform for your perusal and also summarised at last

1.lspci -vxx

00:02.0 VGA compatible controller: Intel Corporation 82815 CGC
[Chipset Graphics Controller] (rev 04) (prog-if 00 [VGA])
Subsystem: Intel Corporation 82815 CGC [Chipset Graphics Controller]
Flags: bus master, 66MHz, medium devsel, latency 0, IRQ 5
Memory at e0000000 (32-bit, prefetchable) [size=64M]
Memory at ea000000 (32-bit, non-prefetchable) [size=512K]
Capabilities: [dc] Power Management version 2
00: 86 80 32 11 07 00 b0 02 04 00 00 03 00 00 00 00
10: 08 00 00 e0 00 00 00 ea 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 32 11
30: 00 00 00 00 dc 00 00 00 00 00 00 00 05 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 22 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

2.register dump with out helper module insertion.
(comments added for easier understanding.)
display is correct for "./vgatest 10"--640 X 480 X256 mode

init: id is 1132
linear_base is E0000000
mmio_base is EA000000
mode 3 available in svga modes; prv_mode: 0
mode 10 not available in svga modes; prv_mode: 0
****i810.c: set mode in svgalib timings success
****i810.c: mode timing standard params pixel clock-25175-6257
HDisplay-640-280
HSyncStart-664-298
HSyncEnd-760-2F8
HTotal-800-320
VDisplay-480-1E0
VSyncStart-491-1EB
VSyncEnd-493-1ED
VTotal-525-20D
flags-100
****i810.c: setting modetimings
****i810.c: CrtcVTotal= 525
ExtVertTotal= 2
CrtcVDisplay= 480
ExtVertDispEnd= 1
CrtcVSyncStart= 491
ExtVertSyncStart= 1
CrtcVSyncStart= 491
ExtVertBlankStart= 1
CrtcHTotal= 800
ExtHorizTotal= 0
CrtcHSyncEnd= 760
ExtHorizBlank= 1
Width: 640 Height: 480 Colors: 256 Mem:0
DisplayStartRange: 7ffffh Maxpixels: 524288 Blit: NO
static unsigned char regs[96] = {
0x5F,0x4F,0x52,0x9F,0x53,0x1F,0x0B,0x3E, /* CR00-CR18 */
0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,
0xEB,0x2D,0xDF,0x28,0x00,0xEB,0xEC,0xC3,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, /* AR00-AR15 */
0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,
0x41,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F, /* GR00-GR05 */
0xFF,
0x03,0x01,0x0F,0x00,0x0E, /* SR00-SR05 */
0xEF, /* MISC_OUT */
/* Extended (count = 0x24) */
0x02,0x00,0x12,0x00,0x2C,0x00,0x09,0x00,
0x40,0x05,0x01,0x00,0x02,0x01,0x01,0x01,
0x00,0x01,0x00,0x00,0x00,0x00,0x11,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x17,0xD3,0x10,0x22,
};
*******GRAPHICS RELATED USEFUL INFO**********
regs[50] 0X40 256 COLOR SHIFT MODE
MEMORY MAP SELECT regs[51] bits 3 2 are 0 1
64 K region A0000-AFFFF
*******SEQUENCER RELATED USEFUL INFO**********
regs[55] 0X01 8 DOTS MODE
regs[55] 0X01 640/720 MODE
EXTENDED MEMORY ENABLED FOR CHARACTER MAP SELECTION
***********CRT RELATED USEFUL INFO*************
HORIZONTAL TOTAL regs[0]=0X5F 800
END HORIZONTAL DISPLAY regs[1]=0X4F AT 632 ACTIVE DISPLAY ENDS
HORIZONTAL BLANKING STARTS AT 0X52 656
regs[3] 0X9F bit 4-0 0X1f
regs[5] 0X1F temp1 0X0 bit 5 0
temp1 after rotate right by 2 0X0 bit 5 0
temp with all 6 bits 0X1F
HORIZONTAL BLANKING ENDS AT 0X5F 760 ON NEXT LINE
HORIZONTAL RETRACE STARTS AT regs[4] 0X53 664
regs[5] 0X1F bit 4-0 0X1F
HORIZONTAL RETRACE ENDS AT 0X5F 760
regs[7] 0X3E bit 0(VT8) 0 temp2 0X0000
regs[7] 0X3E bit 5(VT9) 1 temp2 with VT9 VT8 0X0002
temp2 after left shifting by 8 0X0200
temp2 after including regs[6]=0X0B is 0X020B
VERTICAL TOTAL 523 SCAN LINES
regs[7] 0X3E bit 2(VRS8) 1 temp2 0X0001
regs[7] 0X3E bit 7(VRS9) 0 temp2 with VRS9 VRS8 0X0001
temp2 after left shifting by 8 0X0100
temp2 after including regs[0X10]=0XEB is 0X01EB
VERTICAL RETRACE STARTS AT 0X1EB 491
temp2 01EB temp 0D
VERTICAL RETRACE ENDS AT regs[0X11] 0X2D 493
regs[7] 0X3E bit 1(VDE8) 1 temp2 0X0001
regs[7] 0X3E bit 6(VDE9) 0 temp2 with VDE9 VDE8 0X0001
temp2 after left shifting by 8 0X0100
temp2 after including regs[0X12]=0XDF is 0X01DF
VERTICAL DISPLAY ENDS AT 0X1DF 479
OFFSET IS 40
WORD/BYTE FIELD TO DECIDE MODE
regs[7] 0X3E bit 3(VBS8) 1 temp2 0X0001
regs[9] 0X40 bit 5(VBS8) 0 temp2 with VBS9 VBS8 0X0001
temp2 after left shifting by 8 0X0100
temp2 after including regs[0X15]=0XEB is 0X01EB
VERTICAL BLANKING STARTS AT 0X1EB 491
VERTICAL BLANKING ENDS AT 0XEC 236
regs[0x17] 0XC3 bit 7 1 SYNC ENABLED
regs[0x17] 0XC3 bit 6 1 BYTE MODE ENABLED--Memory Address Size = 1
regs[59] 0XEF bit 7 1 POSITIVE VERTICAL RETRACE SYNC PULSE ENABLED
regs[59] 0XEF bit 6 1 POSITIVE HORIZONTAL RETRACE SYNC PULSE ENABLED
regs[59] 0XEF bits 3 2 are 1 1 PROGRAMMED CLOCK USED
regs[59] 0XEF bit 1 1 RAM ENABLED
regs[59] 0XEF bit 0 1 IO ADDRESS SELECT ENABLED
mode 3 available in svga modes; prv_mode: 10

3.register dump with helper module usage.
(comments added for easier understanding.)
display repeated pattern for "./vgatest 10"--640 X 480 X256 mode

init: id is 1132
linear_base is E0000000
mmio_base is EA000000
mode 3 available in svga modes; prv_mode: 0
mode 10 not available in svga modes; prv_mode: 0
****i810.c: set mode in svgalib timings success
****i810.c: mode timing standard params pixel clock-25175-6257
HDisplay-640-280
HSyncStart-664-298
HSyncEnd-760-2F8
HTotal-800-320
VDisplay-480-1E0
VSyncStart-491-1EB
VSyncEnd-493-1ED
VTotal-525-20D
flags-100
****i810.c: setting modetimings
****i810.c: CrtcVTotal= 525
ExtVertTotal= 2
CrtcVDisplay= 480
ExtVertDispEnd= 1
CrtcVSyncStart= 491
ExtVertSyncStart= 1
CrtcVSyncStart= 491
ExtVertBlankStart= 1
CrtcHTotal= 800
ExtHorizTotal= 0
CrtcHSyncEnd= 760
ExtHorizBlank= 1
Width: 640 Height: 480 Colors: 256 Mem:0
DisplayStartRange: 3fffffh Maxpixels: 4194304 Blit: NO
static unsigned char regs[96] = {
0x5F,0x4F,0x52,0x9F,0x53,0x1F,0x0B,0x3E, /* CR00-CR18 */
0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,
0xEB,0x2D,0xDF,0x28,0x00,0xEB,0xEC,0xC3,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, /* AR00-AR15 */
0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,
0x41,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F, /* GR00-GR05 */
0xFF,
0x03,0x01,0x0F,0x00,0x0E, /* SR00-SR05 */
0xEF, /* MISC_OUT */
/* Extended (count = 0x24) */
0x01,0x00,0x12,0x00,0x2C,0x00,0x09,0x00,
0x40,0x0A,0x01,0x00,0x02,0x01,0x01,0x01,
0x00,0x01,0x00,0x00,0x00,0x00,0x11,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x17,0xD3,0x10,0x22,
};
*******GRAPHICS RELATED USEFUL INFO**********
regs[50] 0X40 256 COLOR SHIFT MODE
MEMORY MAP SELECT regs[51] bits 3 2 are 0 1
64 K region A0000-AFFFF
*******SEQUENCER RELATED USEFUL INFO**********
regs[55] 0X01 8 DOTS MODE
regs[55] 0X01 640/720 MODE
EXTENDED MEMORY ENABLED FOR CHARACTER MAP SELECTION
***********CRT RELATED USEFUL INFO*************
HORIZONTAL TOTAL regs[0]=0X5F 800
END HORIZONTAL DISPLAY regs[1]=0X4F AT 632 ACTIVE DISPLAY ENDS
HORIZONTAL BLANKING STARTS AT 0X52 656
regs[3] 0X9F bit 4-0 0X1f
regs[5] 0X1F temp1 0X0 bit 5 0
temp1 after rotate right by 2 0X0 bit 5 0
temp with all 6 bits 0X1F
HORIZONTAL BLANKING ENDS AT 0X5F 760 ON NEXT LINE
HORIZONTAL RETRACE STARTS AT regs[4] 0X53 664
regs[5] 0X1F bit 4-0 0X1F
HORIZONTAL RETRACE ENDS AT 0X5F 760
regs[7] 0X3E bit 0(VT8) 0 temp2 0X0000
regs[7] 0X3E bit 5(VT9) 1 temp2 with VT9 VT8 0X0002
temp2 after left shifting by 8 0X0200
temp2 after including regs[6]=0X0B is 0X020B
VERTICAL TOTAL 523 SCAN LINES
regs[7] 0X3E bit 2(VRS8) 1 temp2 0X0001
regs[7] 0X3E bit 7(VRS9) 0 temp2 with VRS9 VRS8 0X0001
temp2 after left shifting by 8 0X0100
temp2 after including regs[0X10]=0XEB is 0X01EB
VERTICAL RETRACE STARTS AT 0X1EB 491
temp2 01EB temp 0D
VERTICAL RETRACE ENDS AT regs[0X11] 0X2D 493
regs[7] 0X3E bit 1(VDE8) 1 temp2 0X0001
regs[7] 0X3E bit 6(VDE9) 0 temp2 with VDE9 VDE8 0X0001
temp2 after left shifting by 8 0X0100
temp2 after including regs[0X12]=0XDF is 0X01DF
VERTICAL DISPLAY ENDS AT 0X1DF 479
OFFSET IS 40
WORD/BYTE FIELD TO DECIDE MODE
regs[7] 0X3E bit 3(VBS8) 1 temp2 0X0001
regs[9] 0X40 bit 5(VBS8) 0 temp2 with VBS9 VBS8 0X0001
temp2 after left shifting by 8 0X0100
temp2 after including regs[0X15]=0XEB is 0X01EB
VERTICAL BLANKING STARTS AT 0X1EB 491
VERTICAL BLANKING ENDS AT 0XEC 236
regs[0x17] 0XC3 bit 7 1 SYNC ENABLED
regs[0x17] 0XC3 bit 6 1 BYTE MODE ENABLED--Memory Address Size = 1
regs[59] 0XEF bit 7 1 POSITIVE VERTICAL RETRACE SYNC PULSE ENABLED
regs[59] 0XEF bit 6 1 POSITIVE HORIZONTAL RETRACE SYNC PULSE ENABLED
regs[59] 0XEF bits 3 2 are 1 1 PROGRAMMED CLOCK USED
regs[59] 0XEF bit 1 1 RAM ENABLED
regs[59] 0XEF bit 0 1 IO ADDRESS SELECT ENABLED
mode 3 available in svga modes; prv_mode: 10

SUMMARY

/*****************************dmesg_laptop_kernel*********************************/
Linux agpgart interface v0.101 (c) Dave Jones
agpgart: Detected an Intel 945GM Chipset.
agpgart: Detected 7932K stolen memory.
agpgart: AGP aperture is 256M @ 0xd0000000
/*********************************************************************************/
/*****************************dmesg_laptop_svgalib_helper*************************/
svgalib_helper: device1: vendor:8086 id:27a2
device1: region0, base=fc100000 len=524288 type=0
device1: region1, base=00001800 len=-65520 type=1
device1: region2, base=d0000000 len=268435456 type=8
device1: region3, base=fc200000 len=262144 type=0/*********************************************************************************/

/******************************lspci -v _laptop***********************************/
00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS/940GML Express Integrated Graphics Controller (rev 03) (prog-if 00 [VGA])
Subsystem: Unknown device 4352:6886
Flags: bus master, fast devsel, latency 0, IRQ 11
Memory at fc100000 (32-bit, non-prefetchable) [size=512K]
I/O ports at 1800 [size=8]

Memory at d0000000 (32-bit, prefetchable) [size=256M]
Memory at fc200000 (32-bit, non-prefetchable) [size=256K]
Capabilities: [90] Message Signalled Interrupts: 64bit- Queue=0/0 Enable-
Capabilities: [d0] Power Management version 2
/*********************************************************************************/


/******************************dmesg_i815CGCpc_kernel************************************/
Linux agpgart interface v0.101 (c) Dave Jones
agpgart: Detected an Intel i815 Chipset.
agpgart: AGP aperture is 64M @ 0xe0000000
/*********************************************************************************/
/****************************dmesg_i815CGCpc_svgalib_helper***********************/
svgalib_helper: Initializing, version 1.9.25
svgalib_helper: device1: vendor:8086 id:1132
device1: region0, base=e0000000 len=67108864 type=8
device1: region1, base=ea000000 len=524288 type=0
/*********************************************************************************/

/******************************lspci -v_i815CGCpc*********************************/
00:02.0 VGA compatible controller: Intel Corporation 82815 CGC [Chipset Graphics Controller] (rev 04) (prog-if 00 [VGA])
Subsystem: Intel Corporation 82815 CGC [Chipset Graphics Controller]
Flags: bus master, 66MHz, medium devsel, latency 0, IRQ 5
Memory at e0000000 (32-bit, prefetchable) [size=64M]
Memory at ea000000 (32-bit, non-prefetchable) [size=512K]
Capabilities: [dc] Power Management version 2
/*********************************************************************************/

Help needed: please explain me meaning of first two entries of dmesg of laptop. (those are not present pc's dmesg.) the svgalib_helper module (that acquires frame buffer mapped in to cpu address space for VGA operations) is able to work fine on laptop but not with my pc with i815M chipset graphics controller.

Last edited by vijayabcdef; 05-17-2011 at 09:49 AM. Reason: elaborating the problem statement
 
  


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