I want to be able to take a user specified file as an input variable and use this to create a target file using a Makefile.

For instance, if a user types:

make test,

I want this Makefile to take 'test' and create an executable test.out.

Questions:

1. What is the proper syntax to use to get collect the second argument from a command line string?

2. Is it possible to have the Makefile target be a variable?
E.g

$(SOURCE_FILE): $(SOURCE_FILE).o
gcc -o $(SOURCE_FILE).out $(SOURCE_FILE).o?

If not, any tips on how I can accomplish this?

Thanks in advance?

Klaus