makefile targets
 

I am trying to set an environment variable just before in a makefile target, just before I attempt to compile.

ie.

target: MYVAR=-DSOMETHING; ./exe_name

./exe_name: $(CPP_SOURCES:cpp=o)
gcc -o ./exe_name ..........

$(CPP_SOURCES:cpp=o): $(CPP_SOURCES)
gcc -o $*.o -c $*.cpp $(MYVAR)

So that the define can be picked up at compile time. it will be a different define for each target i am trying to build.

Is it possible to do this at all?

Cheers, Dan.

when posting code--especially whitespace-sensitive code (such as makefiles and python scripts)--please put the code in `code tags' ([ code ] <your code goes here> [ /code ] -- but without the spaces near brackets).

In fact, I would recommend code tags for any files contents or program I/O--it mostly acts like the HTML <pre> tag.

(Of course, if it's PHP, use [ php ] instead :))

In that way, people can more easily understand what you're trying to say, and help you better.

--Jonas