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Old 07-11-2005, 10:56 AM   #1
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Registered: Dec 2004
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makefile targets

I am trying to set an environment variable just before in a makefile target, just before I attempt to compile.


target: MYVAR=-DSOMETHING; ./exe_name

./exe_name: $(CPP_SOURCES:cpp=o)
gcc -o ./exe_name ..........

gcc -o $*.o -c $*.cpp $(MYVAR)

So that the define can be picked up at compile time. it will be a different define for each target i am trying to build.

Is it possible to do this at all?

Cheers, Dan.
Old 07-11-2005, 03:28 PM   #2
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Registered: Jul 2004
Location: Denmark
Distribution: Ubuntu, Debian
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when posting code--especially whitespace-sensitive code (such as makefiles and python scripts)--please put the code in `code tags' ([ code ] <your code goes here> [ /code ] -- but without the spaces near brackets).

In fact, I would recommend code tags for any files contents or program I/O--it mostly acts like the HTML <pre> tag.

(Of course, if it's PHP, use [ php ] instead )

In that way, people can more easily understand what you're trying to say, and help you better.



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