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Old 01-04-2018, 11:50 AM   #1
LXer
LXer NewsBot
 
Registered: Dec 2005
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LXer: Reading privileged memory with a side-channel


Published at LXer:

We have discovered that CPU data cache timing can be abused to efficiently leak information out of mis-speculated execution, leading to (at worst) arbitrary virtual memory read vulnerabilities across local security boundaries in various contexts. Variants of this issue are known to affect many modern processors, including certain processors by Intel, AMD and ARM.

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