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Old 06-26-2017, 08:28 AM   #1
kjhambrick
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Question Broken HyperThreading in SkyLake and Kaby Lake Processors.


all --

ppencho mentioned the intel processor hyperthreading bug in Requests for -current (20151216)

I have an Intel i7 6700k ( Model 94 ; Stepping 3 ) which is affected but can be fixed with a microcode update.

I see there are SlackBuilds for iucode_tool and intel-microcode

Aside from the intel-microcode/README recommendation to read the early-microcode.txt file, does anyone have any advice for installing and running intel-microcode ?

Thanks in Advance !

-- kjh
 
Old 06-26-2017, 03:41 PM   #2
55020
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Yes iucode_tool and intel-microcode are what you need.

(1) build and install iucode_tool from SBo

(2) build and install intel-microcode from SBo, this creates a file /boot/intel-ucode.cpio

(3) If you do not use an initrd at the moment, use /boot/intel-ucode.cpio as your initrd -- for example, with lilo you will have to modify /etc/lilo.conf and then re-run /sbin/lilo, or with elilo you will have to edit /boot/efi/EFI/Slackware/elilo.conf and copy /boot/intel-ucode.cpio to /boot/efi/EFI/Slackware/

(4) If you do use an initrd (presumably /boot/initrd.gz) do this:

Code:
cp /boot/initrd.gz /tmp
cat /boot/intel-ucode.cpio /tmp/initrd.gz > /boot/initrd.gz
and then (important) re-run /sbin/lilo, or copy the new /boot/initrd.gz to /boot/efi/EFI/Slackware, or do whatever your own boot loader wants. And you will have to repeat this after every time you run mkinitrd.

I wonder, if someone added support to mkinitrd for /boot/intel-ucode.cpio and sent a patch to volkerdi, would that be welcomed?
 
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Old 06-26-2017, 04:43 PM   #3
volkerdi
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Quote:
Originally Posted by 55020 View Post
I wonder, if someone added support to mkinitrd for /boot/intel-ucode.cpio and sent a patch to volkerdi, would that be welcomed?
More than likely, yes. If you do, cc: rworkman on it as well. Thanks!
 
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Old 06-26-2017, 05:12 PM   #4
kjhambrick
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Thanks 55020.

Installed iucode_tool and intel-microcode and set up the 4.4.74.kjh huge kernel with
Code:
  initrd = /boot/intel-ucode.cpio
I did leave a 'fallback'

reran lilo and I am rebooting now ...

will let you know in a minute or two.

-- kjh
 
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Old 06-26-2017, 05:26 PM   #5
kjhambrick
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55020 --

Everything seems to work as advertized.

1. Build and installed the two packages:
Code:
# ver iucode_tool microcode
-rw-r--r-- 1 root root 1251 Jun 26 08:05 /var/log/packages/iucode_tool-2.1.2-x86_64-1_SBo               
-rw-r--r-- 1 root root 3893 Jun 26 16:04 /var/log/packages/intel-microcode-20170511-noarch-1_SBo
2. Cloned the lilo.conf stanza for the 4.4.74.kjh HUGE Kernel and added the intel-uode.cpio initrd:
Code:
image    = /boot/vmlinuz-huge-4.4.74.kjh
  root   = /dev/sda3
  initrd = /boot/intel-ucode.cpio
  label  = Linux4474.uc
  read-only
image    = /boot/vmlinuz-huge-4.4.74.kjh
  root   = /dev/sda3
  label  = Linux4474.kjh
  read-only
Rebooted and selected linux4474.uc ... booted fine.

I am a little confused though, I installed the 2017-05-11 intel-microcode package and yet dmesg reports version 2017-04-09 ???
Code:
# dmesg |grep microcode |less
[    0.000000] microcode: CPU0 microcode updated early to revision 0xba, date = 2017-04-09
[    0.047240] microcode: CPU1 microcode updated early to revision 0xba, date = 2017-04-09
[    0.051590] microcode: CPU2 microcode updated early to revision 0xba, date = 2017-04-09
[    0.055939] microcode: CPU3 microcode updated early to revision 0xba, date = 2017-04-09
[    7.114335] microcode: CPU0 sig=0x506e3, pf=0x2, revision=0xba
[    7.136553] microcode: CPU1 sig=0x506e3, pf=0x2, revision=0xba
[    7.158151] microcode: CPU2 sig=0x506e3, pf=0x2, revision=0xba
[    7.179289] microcode: CPU3 sig=0x506e3, pf=0x2, revision=0xba
[    7.200167] microcode: CPU4 sig=0x506e3, pf=0x2, revision=0xba
[    7.220689] microcode: CPU5 sig=0x506e3, pf=0x2, revision=0xba
[    7.240720] microcode: CPU6 sig=0x506e3, pf=0x2, revision=0xba
[    7.260178] microcode: CPU7 sig=0x506e3, pf=0x2, revision=0xba
[    7.279637] microcode: Microcode Update Driver: v2.01 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
Will read some more on it.

-- kjh
 
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Old 06-26-2017, 05:40 PM   #6
D1ver
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One of the Debian guys wrote a quick perl script to see if you are affected by this. https://lists.debian.org/debian-deve.../msg00309.html

You could use that to see if the microcode update fixed your problem. I am apparently affected as well but haven't had a chance to try the update from SBo.

Edit:
Ok, thanks 55020 for those instructions! I went through with the update and apparently everything is fixed now.

Last edited by D1ver; 06-26-2017 at 06:01 PM.
 
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Old 06-26-2017, 06:01 PM   #7
kjhambrick
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Thanks D1ver !

I cut-n-pasted the perl script into a file and these are the results for my CPU:
Code:
# mkcmd check-cpu-for-HT-bug.pl
  
  <<cut-n-pasted the code from your link >>

./check-cpu-for-HT-bug.pl
cpu 0: Your CPU is affected, but your microcode is new enough
cpu 1: Your CPU is affected, but your microcode is new enough
cpu 2: Your CPU is affected, but your microcode is new enough
cpu 3: Your CPU is affected, but your microcode is new enough
cpu 4: Your CPU is affected, but your microcode is new enough
cpu 5: Your CPU is affected, but your microcode is new enough
cpu 6: Your CPU is affected, but your microcode is new enough
cpu 7: Your CPU is affected, but your microcode is new enough
I also found a releasenote file in Intel's microcode-20170511.tgz file which didn't get copied into /usr/doc/intel-microcode-20170511/ by the intel-microcode.SlackBuild

I'll 'fix' the SlackBuild and report upstream to the maintainer.

Based on all of the above, although I've got the HT bug, I've got the fix for my SkyLake 6700K

-- kjh

Code:
# mkdir tmp
# tar -xvf ../microcode-20170511.tgz releasenote
# cat releasenote

Intel Processor Microcode Package for Linux
20170511 Release

-- Updates --
BDX-ML B0/M0/R0 (06-4f-01:ef) b00001f->b000021
Skylake D0 (06-4e-03:c0) 9e->ba
Broadwell ULT/ULX E/F-step (06-3d-04:c0) 24->25
ULT Cx/Dx (06-45-01:72) 1f->20
Crystalwell Cx (06-46-01:32) 16->17
Broadwell Halo E/G-step (06-47-01:22) 16->17
HSX EX E0 (06-3f-04:80) d->f
Skylake R0 (06-5e-03:36) 9e->ba
Haswell Cx/Dx (06-3c-03:32) 20->22
HSX C0 (06-3f-02:6f) 39->3a

-- Microcode update instructions --
This package contains Intel microcode files in two formats:
* microcode.dat
* intel-ucode directory 

microcode.dat is in a traditional text format. It is still used in some
Linux distributions. It can be updated to the system through the old microcode
update interface which is avaialble in the kernel with
CONFIG_MICROCODE_OLD_INTERFACE=y.

To update the microcode.dat to the system, one need:
1. Ensure the existence of /dev/cpu/microcode
2. Write microcode.dat to the file, e.g.
  dd if=microcode.dat of=/dev/cpu/microcode bs=1M

intel-ucode dirctory contains binary microcode files named in
family-model-stepping pattern. The file is supported in most modern Linux
distributions. It's generally located in the /lib/firmware directory,
and can be updated throught the microcode reload interface.

To update the intel-ucode package to the system, one need:
1. Ensure the existence of /sys/devices/system/cpu/microcode/reload
2. Copy intel-ucode directory to /lib/firmware, overwrite the files in
/lib/firmware/intel-ucode/
3. Write the reload interface to 1 to reload the microcode files, e.g.
  echo 1 > /sys/devices/system/cpu/microcode/reload
 
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Old 06-26-2017, 06:41 PM   #8
55020
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Quote:
Originally Posted by kjhambrick View Post
I am a little confused though, I installed the 2017-05-11 intel-microcode package and yet dmesg reports version 2017-04-09 ???
That's right. See https://lists.debian.org/debian-deve.../msg00308.html
The relevant part is:
Quote:
Fixes for processors with signatures[1] 0x406E3 and 0x506E3 are
available in the Intel public Linux microcode release 20170511. This
will fix only Skylake processors with model 78 stepping 3, and model 94 stepping 3. The fixed microcode for these two processor models reports
revision 0xb9/0xba, or higher.

Apparently, these errata were fixed by microcode updates issued in early
April/2017. Based on this date range, microcode revision 0x5d/0x5e (and
higher) for Kaby Lake processors with signatures 0x806e9 and 0x906e9
*might* fix the issue. We do not have confirmation about which
microcode revision fixes Kaby Lake at this time.


Related processor signatures and microcode revisions:
Skylake : 0x406e3, 0x506e3 (fixed in revision 0xb9/0xba and later,
public fix in linux microcode 20170511)
Skylake : 0x50654 (no information, erratum listed)
Kaby Lake : 0x806e9, 0x906e9 (defect still exists in revision 0x48,
fix available as a BIOS/UEFI update)
Repeat: the public microcode is *not* known to fix Skylake 0x50654 and Kaby Lake 0x806e9, 0x906e9. Vendor BIOS updates might have a fix, if you're lucky and the vendor has bothered.

Ryzen is looking iffy too at the moment btw. https://community.amd.com/thread/215773

Edit:
Quote:
Originally Posted by D1ver View Post
One of the Debian guys wrote a quick perl script to see if you are affected by this. https://lists.debian.org/debian-deve.../msg00309.html
That script doesn't work properly, see the subsequent message in the same thread: https://lists.debian.org/debian-deve.../msg00318.html

Last edited by 55020; 06-26-2017 at 06:51 PM.
 
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Old 06-26-2017, 07:25 PM   #9
D1ver
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Quote:
That script doesn't work properly, see the subsequent message in the same thread: https://lists.debian.org/debian-deve.../msg00318.html
Interesting, so it can report some false positives. In my case it reported that I was affected before the update, and am fixed after the update.. So it is still kinda useful.
 
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Old 06-27-2017, 07:43 AM   #10
willysr
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Too bad mine is still not yet fixed
Kaby Lake : 0x806e9, 0x906e9 (defect still exists in revision 0x48,
fix available as a BIOS/UEFI update)
 
Old 06-27-2017, 07:51 AM   #11
kjhambrick
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All --

Installed last night's Official Slackware 4.4.74 Generic and Huge Kernels.

The methods outlined above by 55020 worked perfectly ( as expected )

Thanks all !

-- kjh

# this is 4.4.74 Generic:
Code:
# dmesg |grep microcode

[    0.000000] microcode: CPU0 microcode updated early to revision 0xba, date = 2017-04-09
[    0.042896] microcode: CPU1 microcode updated early to revision 0xba, date = 2017-04-09
[    0.047244] microcode: CPU2 microcode updated early to revision 0xba, date = 2017-04-09
[    0.051592] microcode: CPU3 microcode updated early to revision 0xba, date = 2017-04-09
[    6.826191] microcode: CPU0 sig=0x506e3, pf=0x2, revision=0xba
[    6.849964] microcode: CPU1 sig=0x506e3, pf=0x2, revision=0xba
[    6.873177] microcode: CPU2 sig=0x506e3, pf=0x2, revision=0xba
[    6.895983] microcode: CPU3 sig=0x506e3, pf=0x2, revision=0xba
[    6.918548] microcode: CPU4 sig=0x506e3, pf=0x2, revision=0xba
[    6.940754] microcode: CPU5 sig=0x506e3, pf=0x2, revision=0xba
[    6.962415] microcode: CPU6 sig=0x506e3, pf=0x2, revision=0xba
[    6.983538] microcode: CPU7 sig=0x506e3, pf=0x2, revision=0xba
[    7.004639] microcode: Microcode Update Driver: v2.01 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
# this is 4.4.74 Huge:
Code:
# dmesg |grep microcode

[    0.000000] microcode: CPU0 microcode updated early to revision 0xba, date = 2017-04-09
[    0.047677] microcode: CPU1 microcode updated early to revision 0xba, date = 2017-04-09
[    0.052011] microcode: CPU2 microcode updated early to revision 0xba, date = 2017-04-09
[    0.056358] microcode: CPU3 microcode updated early to revision 0xba, date = 2017-04-09
[    7.102552] microcode: CPU0 sig=0x506e3, pf=0x2, revision=0xba
[    7.124597] microcode: CPU1 sig=0x506e3, pf=0x2, revision=0xba
[    7.145983] microcode: CPU2 sig=0x506e3, pf=0x2, revision=0xba
[    7.166949] microcode: CPU3 sig=0x506e3, pf=0x2, revision=0xba
[    7.187648] microcode: CPU4 sig=0x506e3, pf=0x2, revision=0xba
[    7.207990] microcode: CPU5 sig=0x506e3, pf=0x2, revision=0xba
[    7.227804] microcode: CPU6 sig=0x506e3, pf=0x2, revision=0xba
[    7.247087] microcode: CPU7 sig=0x506e3, pf=0x2, revision=0xba
[    7.266139] microcode: Microcode Update Driver: v2.01 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
 
Old 06-27-2017, 12:08 PM   #12
phenixia2003
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Hello,

Below is a simple patch for mkinitrd that adds option -P to prepend the ouput image with a given microcode cpio archive.

This patch works with mkinitrd from 14.1 to -current.

For instance, to prepend the output image with intel microcode /boot/intel-ucode.cpio installed with package intel-microcode from SBo, pass the option -P /boot/intel-ucode.cpio to mkinitrd. Example (from one of my Slackware installations, 14.1 in this case) :

Code:
$ mkinitrd -c \
        -k \
        3.10.103 \
        -f ext4 \
        -r /dev/disk/by-label/SYSMAIN.ROOT \
        -m usb-storage:ums-realtek:ehci-hcd:ehci-pci:usbhid:hid_generic:xhci-hcd:mbcache:jbd2:ext4 \
        -h /dev/disk/by-label/SYSMAIN.SWAP \
        -P /boot/intel-ucode.cpio \
        -u \
        -s /boot/initrd/initrd-tree-generic-3.10.103-with-intel-ucode \
        -o /boot/initrd-generic-3.10.103-with-intel-ucode.gz
You can check that microcode cpio has been prepended by running the command cpio -it < boot/<your-initrd-name>.gz. Example:
Code:
$ cpio -it < /boot/initrd-generic-3.10.103-with-intel-ucode.gz
kernel
kernel/x86
kernel/x86/microcode
kernel/x86/microcode/.enuineIntel.align.0123456789abc
kernel/x86/microcode/GenuineIntel.bin
1922 blocks
On reboot, to check that microcode is updated early, run the command dmesg as below :
Code:
$ dmesg | head -n 1
[    0.000000] CPU0 microcode updated early to revision 0x1c, date = 2015-02-26
Here is the patch:

Code:
--- mkinitrd.org	2017-06-27 17:27:46.140008037 +0200
+++ mkinitrd	2017-06-27 17:29:53.475013719 +0200
@@ -102,6 +102,7 @@
   -B      Add /sbin/btrfs to enable scanning for a root filesystem that is
           part of a Btrfs multi-device filesystem.
   -M      Add the files in /etc/modprobe.d/ and /lib/modprobe.d/ to the initrd
+  -P      Prepend the output image with the microcode CPIO archive given in arguments.
   -R      Add support for RAID partitions
   -V      Display version number
 
@@ -180,6 +181,11 @@
     rm -f $OUTPUT_IMAGE
     find . | cpio -o -H newc | gzip -9c > $OUTPUT_IMAGE
   )
+
+  if [ ! -z "${MICROCODE_ARCH}" ] ; then
+    cat ${MICROCODE_ARCH} ${OUTPUT_IMAGE} > ${OUTPUT_IMAGE}.2
+    mv ${OUTPUT_IMAGE}.2 ${OUTPUT_IMAGE}
+  fi
   echo "$OUTPUT_IMAGE created."
   echo "Be sure to run lilo again if you use it."
 }
@@ -371,6 +377,16 @@
       MODCONF=1
       shift
       ;;
+    -P)
+      # canonicalize filename:
+      MICROCODE_ARCH="$(readlink -m $2)"
+      if [ ! -e "${MICROCODE_ARCH}" ] ; then
+        echo "Error, the microcode cpio archive ${MICROCODE_ARCH} does not exist."
+        exit 1
+      fi
+      shift 2
+    ;;
+
     -R)
       RAID=1
       shift
--
SeB
 
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Old 06-29-2017, 08:19 PM   #13
kjhambrick
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Woo Hoo phenixia2003 !

Check out this evening's Slackware ChangeLogs:

Code:
patches/packages/mkinitrd-1.4.10-x86_64-1_slack14.2.txz:  Upgraded.
  Added support for -P option and MICROCODE_ARCH in mkinitrd.conf to specify
  a microcode archive to be prepended to the initrd for early CPU microcode
  patching by the kernel. Thanks to SeB.
Now I will have to re-rewrite my do-mkinitrd_command_generator.sh to pass along your new -P option to mkinitrd for my CPU

Thank you for sharing SeB !

-- kjh

p.s. I just did a timing test on 4.4.75.kjh-HUGE vs 4.4.75.kjh-GENERIC and HUGE does boot 1-sec faster:

Code:
[root@kjhlt6 tmp]# tail 4.4.75.kjh-GENERIC.dmesg.txt
[   29.344599] alx 0000:3c:00.0 eth0: NIC Up: 1 Gbps Full
[   29.535666] userif-5: sent link down event.
[   29.535667] userif-5: sent link up event.
[   29.535680] userif-0: sent link down event.
[   29.535681] userif-0: sent link up event.
[   31.357374] alx 0000:3c:00.0 eth0: NIC Up: 1 Gbps Full
[   31.551358] userif-5: sent link down event.
[   31.551359] userif-5: sent link up event.
[   31.551384] userif-0: sent link down event.
[   31.551386] userif-0: sent link up event.

[root@kjhlt6 tmp]# tail 4.4.75.kjh-HUGE.dmesg.txt
[   28.347346] alx 0000:3c:00.0 eth0: NIC Up: 1 Gbps Full
[   28.538820] userif-5: sent link down event.
[   28.538822] userif-5: sent link up event.
[   28.538832] userif-0: sent link down event.
[   28.538833] userif-0: sent link up event.
[   30.369898] alx 0000:3c:00.0 eth0: NIC Up: 1 Gbps Full
[   30.553830] userif-5: sent link down event.
[   30.553831] userif-5: sent link up event.
[   30.553855] userif-0: sent link down event.
[   30.553857] userif-0: sent link up event.

Last edited by kjhambrick; 06-29-2017 at 08:21 PM. Reason: oops ... that timing test was for 55020 !
 
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