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Old 03-15-2011, 04:16 AM   #1
dazzlinggopi
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Lightbulb Why do we need all data structures to be naturally aligned


Hi,
i got the definition of natural alignment from http://www.mjmwired.net/kernel/Docum...ory-access.txt.

From what it says if we are going to access n bytes of data we need the data to be stored at an address evenly divisible by 'n'.

Tested it in fedora 13 with gcc.
this is how the programme looks..
#include<stdio.h>
struct node
{
short a;
int b;
char c;
}x;
struct y
{
char a;
}z;
int main()
{
printf("%d\t %d\n",sizeof(x),sizeof(z));
printf("%x\t%x\t%x\n",&(x.a),&(x.b),&(x.c));
return 0;
}

out put :

./a.out
12 1
804969c 80496a0 80496a4


i can understand that if a machine has 32 databus lines ,since it can access 4bytes once for better performance we restrict the address to be aligned to 4byte boundary this can be applied to 16bit and 64 bit machines .. I guess i am right looking at the o/p of above prgm.

but why should we have natural alignment i don't understand apart from compatibility issues.
Please clarify it for me .. if you are saying it as a hardware limitation explain why..

Please give as eloborated answers as possible ..

Thanks in advance.
 
Old 03-15-2011, 09:03 AM   #2
neonsignal
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Quote from the article you linked "In reality, only a few architectures require natural alignment on all sizes of memory access."

The reason for natural alignment is to guarantee memory alignment no matter what the underlying memory architecture is (and also to have some sort of consistency between the code on different architectures).

Having unaligned accesses is at best a performance cost, and at worst may not be possible. Some processors require operating system support in order to do an unaligned access (ie, they do not even implement unaligned memory access, since it is a waste of silicon resources). The same can also apply to networking hardware.

Since in a high level language the compiler will typically align data structures, it isn't always something you need to be concerned about. You are only going to encounter the issue when using packed structures or recasting pointers and the like. However, it is useful to be aware of this alignment when designing data structures (for example packet headers etc).

Last edited by neonsignal; 03-15-2011 at 09:06 AM.
 
Old 03-16-2011, 02:15 AM   #3
dazzlinggopi
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I know that its for performance and so on ..i wanted to know at which point the processor memory accessing mechanism depends on aligned or unaligned memory address.Some architectures invoke a special set of instructions for unaligned memory access why are they even needed?
if we are going to access 3 bytes of memory we should store it at an address which is evenly divisible by 3... i wanted to know how processor is depending on this ?
 
Old 03-16-2011, 04:58 AM   #4
neonsignal
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Your example of '3 bytes of memory' is not a typical one, most processors have no instructions that would access a unit of 3 bytes. Rather than talk about bytes, think about it in terms of basic units of processor access (typically 1/2/4/8 bytes).

The level at which alignment matters is at the machine code level. Let a simple example be an arbitrary processor, where a 16 bit word of data is being loaded from 16 bit memory into a 16 bit register, over a 16 bit data bus.
Code:
ldw a,[6E63h]
This is an unaligned load, because 6E63h is not a multiple of 2 bytes (16 bits).

If the processor supports unaligned loads, then it will have to load up the word from 0x6E62, throw away the first half and move the second half into the first part of the a register, then load up the word from 0x6E64, throw away the second half and move the first half into the second part of the register. This is not just a major performance penalty, but costs a lot of extra transistors.

If the processor doesn't support unaligned loads, then it doesn't implement the logic to do the above sequence. This makes sense, since there is seldom a need for unaligned loads, they cost extra silicon, they add complexity, their execution time is inconsistent with other instructions, they cause divisibility problems and so on. Instead, the processor might throw an interrupt exception, which enables the operating system to either flag the error, or jump to some code that will perform the above sequence in software.

This affects most processor instructions, since a typical 32 or 64 bit processor will mostly be working on 32 or 64 bit operands (for example, stack access should also be aligned). Indeed, on some RISC processors, even the instructions themselves have to be aligned.

Since the high level code is supposed to be agnostic about the underlying processor and memory system word size, it is useful to have a rule that all memory access is naturally aligned, so that we won't ever have to deal with misalignment. This rule applies to the primitive data types, not to constructed ones (though it does apply to the primitive members of constructs).

Last edited by neonsignal; 03-16-2011 at 05:02 AM.
 
Old 04-08-2011, 10:43 AM   #5
swageo
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Answers are still not conclusive..

There are instructions that load single byte, like movb in x86. If this instruction can read on byte from from memory, why a 2 byte word cannot be read from odd address. ?

I searched the whole net to find an answer, but everyone finally says its requirement from processor.. including docs in intel site..
 
  


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