Hi all.

I am trying to cross compile for a arm processor, from my linux running PC. Here is my Makefile code:

------------------------------------------------------
SOURCES=main.cpp part1.cpp part2.cpp
OBJECTS=${SOURCES:.cpp=.o}
EXECUTABLES=main_tgt
CC=arm-angstrom-linux-gnueabi-g++

all: ${OBJECTS}
${CC} -o ${EXECUTABLES} ${OBJECTS}

parts: ${SOURCES}
${CC} -c ${SOURCES}

clean:
rm ${EXECUTABLE} ${OBJECTS}
---------------------------------------------------------------

As you see i want to compile with the arm-angstrom...-g++ compiler, but when i do compile the objects files made is for Intel80386 ????.. And therefore the executable never gets made?.

Someone know why the generated object files becomes Inten80386 objectfiles instead of arm?

Although you posted this as a question about Makefiles, I question whether you actually have a properly installed ARM Angstrom cross toolchain. Can you run the specified compiler outside of a Makefile, and still create ARM binaries? How are you determining that the binaries are x86 format?

--- rod.

I have compiled before without using Makefile, and then it compiles just fine. Actually I have also compiled a "Hello_world.cpp" with a Makefile similar to the one shown, just with Hello_world.cpp as the only document in the variable SOURCES.

I determine the file format by typing:
>$ file main.o

In my project folder I actually have 2 makefiles: Makefile.host and Makefile.target where Makefile.host works perfectly fine, but Makefile.host wont

And I remember to delete all the object files before running a Makefile.

Okay, when the make runs, do you see the correct version of gcc being used? Have you removed the old object code (make clean) and re-tried? Is the correct compiler in $PATH (you don't have a fully qualified filespec for $CC).

--- rod.

BTW: you must have mistyped when you wrote: 'Makefile.host works perfectly fine, but Makefile.host wont'

Yes i clean first. And i think that the path is known.. I have attached a screenshot of the terminal error if that help u help me?

Attached Thumbnails

 

Caveat: I don't do any cross-compiling. Forgive me if I misunderstand the process, but...

The output you show indicates that make is relying on implicit rules to create the object files. The implicit rule invokes plain-jane "g++" -- not "arm-angstrom-linux-gnueabi-g++" -- to create the object files.

I assume you need "arm-angstrom-linux-gnueabi-g++" to create those files.

To do so, you need to modify your Makefile and add something like this:
It appears that your "parts" target may have been what you thought would perform this step.

As an alternative to the above, depending on what your ultimate goal is, you could probably just replace your "parts" target definition with:
-or-
The original approach using "%.o : %.cpp" is the more typical/standard way of doing it in my experience.

EDIT:
Also, assuming you're using GNU make, you probably need to add:
Which will make sure that the clean target always executes its target instructions when invoked.

1 members found this post helpful.

I think the OP should consider defining CXX in lieu of using CC, which is for C programs. CXX is interpreted by 'make', along with CXXFLAGS if compiler flags are needed, for building C++ files. This would obviate the need to define a rule to make the object files, since 'make' already has a built-in rule for this.

1 members found this post helpful.

It works!!.. I deleted the parts target and inserted
So thanks! .. But what does the 2 lines exactly?

And where should I insert the ".PHONY : clean" line, so the clean target is called every time I run the makefile?

Oh and one more question: How can I save my object files in an other directory?.. for example if my makefile is in home/user/project1 and I want to save my object files in home/user/project1/target?

The percent character denotes a wildcard. Thus to make foo.o, 'make' looks for foo.cpp. The $< refers to the dependency, which is %.cpp. The -c option instructs the compiler to build only an object (.o) file.

You really should be using CXX, not CC, for building C++ files.

P.S. For example:

I usually place it right before the clean target itself.

But you may have misunderstood what I meant--my wording was poor. Adding ".PHONY : clean" to the Makefile will force make to execute the instructions for the "clean" target everytime you invoke "make clean." That is, the "phony" designation turns off make's internal decision making for whether the target should or should not be updated.

It will not cause make to execute the clean target commands everytime you run make.

You might be able to accomplish what you're thinking by adding the clean target as a dependency to another target. Though, I think the make documentation says that the order of dependency updates is not guaranteed. So doing so might cause the clean instructions to run after other dependencies have been built. Also, by running clean everytime, you eliminate one of the main reasons for using make to begin with: only re-compiling the parts that have been changed since your last compile.

EDIT:
Collecting your object files in another directory will require more work. I recently came across a post on another forum. The second answer (added by anon and edited by Daryl Spitzer) gives a solution to that particular problem with the use of the patsubst() function provided by make.

Okay..

I got it all to work now!.. Thanks to both of you

I gotta say, i rly like the Linux community!