Makefile Problem

nelnel · 07-07-2005, 09:35 PM

Hello, i want to create a simple Makefile to compile a group of cpp file. So i search the information of Makefile from internet. I created a simple Makefile, but don't work as my expectation.

Makefile:
CC = g++
CFLAGS = -L/opt/oracle/product/9.2.0/lib

TARGET = test

OBJS = abc.o strncat.cpp

all: $(TARGET) abc.o

clean:
rm -f $(TARGET) *.o *~ core

$(TARGET): $(OBJS)
$(CC) $(CFLAGS) -o $(TARGET) $(OBJS) $(LIBS)

abc.o: abc.cpp abc.h

I expect the compilation process is:

g++ -c -o abc.o abc.cpp
g++ -L/opt/oracle/product/9.2.0/lib -c -o strncat.o strncat.cpp
g++ -L/opt/oracle/product/9.2.0/lib -o test abc.o strncat.o

but the real output is:

-L/opt/oracle/product/9.2.0/lib

how can i change the Makefile content to call the FLAGS during the compilation of the Obect file?

thx

nelnel · 07-07-2005, 09:37 PM

Sorry i post the wrong code

my expectation is:

g++ -L/opt/oracle/product/9.2.0/lib -c -o abc.o abc.cpp
g++ -L/opt/oracle/product/9.2.0/lib -o test abc.o strncat.cpp

but the real one is

g++ -c -o abc.o abc.cpp
g++ -L/opt/oracle/product/9.2.0/lib -o test abc.o strncat.cpp

thx

Tinkster · 07-07-2005, 11:55 PM

Errrh ... sorry, wrong reponse

Cheers,
Tink

sind · 07-08-2005, 12:53 AM

Hi nelnel,

Looks like you've given make the dependencies for abc.o, but not how to build it. If you don't tell make what command to use, it will use a default one that is chosen according to the source file's extension.

I think changing this:

Code:

abc.o: abc.cpp abc.h

to this:

Code:

abc.o: abc.cpp abc.h
        $(CC) $(CFLAGS) -c -o $@ abc.cpp

will give you the result that you expect.

~sind

nelnel · 07-08-2005, 02:31 AM

THAT's work!!!

thx v.much~~~