Makefile and make depend

Meaculpa · 06-29-2005, 05:53 AM

Hi folks,

I am trying to create a standardized Makefile construct for my projects. Standardized means i do not need to specify the targets all one by one but with pattern matching like

Code:

%.o: %.cc %.h
    $(CXX) ...

Now there comes up a problem: If i got a headerfile named equal as the sourcefile all works right. But if not make will not find a target to compile.
Example:

Code:

...
SOURCES:=main.cc test.cc
HEADERS:=test.h
TARGETDIR:=../objects
 ...

$(TARGETDIR)/%.o: %.cc %.h
    $(CXX) $(CXXFLAGS) -o $@ $<

depend:
    $(CXX) -E -MM $(SOURCES) $(HEADERS) > .depend

This snippet will compile test.cc if test.h is changed. But it will not compile main.cc because there is no header.

Now the question: How can I modify the makefile so that it can check if a header exists and than and only than include it to the rule?

I am grateful for any suggestions

Greetz Mea

jtshaw · 06-30-2005, 03:19 PM

I typically do something like this:

Code:

SOURCES:=test.cc

%.o: %.cc *.h
        $(CXX) $(CXXFLAGS) -o $@ $<

depend:
        $(CXX) -E -MM *.cc > .depend

My typical directory layout will have a subdir for each module of the project. I never have header files inside the subdir that wouldn't be depended on which is why I feel I can safely use *.h. As far as the g++ -MM is conserned... it gets the dependencies based on the includes of a file so it isn't neccesary to have the $(HEADERS) part.

bigearsbilly · 07-01-2005, 07:54 AM

Try this as a start. Simple makefile for multiple source file targets.
Utilises make's in-built rules where possible.

Single directory.
Compile multiple .c .h files into one target.

Just change the target name at the top.
Automagically picks up new source files.

I hope.

Code:

TARGET=blah_blah
#	---------------------------------
#	Standard makefile template
#	just specify the target name above
#	and the make file should sort it
#	all out (hopefully)
#	---------------------------------

INCLUDEFILE = include.mk


# this should appear above the 'include' directive below
# calls for the target and then the cleanup
# =========================================
all: ${TARGET} cleanup 


-include ${INCLUDEFILE}

# ${INCLUDEFILE} should not exist when it's included.
# As it does not exist it is treated as a target.
# Therefore it is created anew each time
# by the appropriate rule, below
# Which finds .c and .h files and calls makedepend for them
# =========================================================

${INCLUDEFILE}:
	@echo "### creating ${INCLUDEFILE}"
	@echo "### creating ${INCLUDEFILE}" > ${INCLUDEFILE}
	-@ echo  *.c|xargs echo SRCFILES = >> ${INCLUDEFILE}
	-@ echo  *.h|xargs echo HFILES = >> ${INCLUDEFILE}
	@  makedepend  -f${INCLUDEFILE} *.c


# (SRCFILES defined in INCLUDEFILE)
# =================================
OBJFILES = ${SRCFILES:.c=.o}


# this is the working target
# ==========================

${TARGET}: ${OBJFILES} 
	${CC} -o $@ ${OBJFILES}

help: print_help cleanup

print_help:
	echo  OBJFILES = ${OBJFILES}
	echo  SRCFILES = ${SRCFILES}
	cat ${INCLUDEFILE}
	

clean:cleanup
	-@ rm -f  *.o 

# we need to delete the INCLUDEFILE otherwise
# new source and header files won't be picked up
# next time
# =========
cleanup:
	@echo "### deleting ${INCLUDEFILE}"
	-@ rm -f  ${INCLUDEFILE}

Mark101 · 03-06-2009, 05:33 AM

I have some trouble with making dependencies.

My makefile concerning build and depend rules look something like:

...
${OBJDIR}/%.o : %.c
gcc <flags> ${INCPATH} -o ${@} $<

depend:
gcc -E -MM ${INCPATH} *.c > ${OBJDIR}/.depend

include ${OBJDIR}/.depend
...

I want to compile my sources and put the objects in a separate directory (= ${OBJDIR} == ../obj/tsm). That works fine. However, I have some trouble making use of the dependency file. When making the depend file the output looks like:

tsm_file.o: tsm_file.c tsm_defs.h tsm_type.h tsm_exts.h
tsm_init.o: tsm_init.c tsm_defs.h tsm_type.h tsm_args.h

But I want it to look like below in order to use it:
../obj/tsm/tsm_file.o: tsm_file.c tsm_defs.h tsm_type.h tsm_exts.h
../obj/tsm/tsm_init.o: tsm_init.c tsm_defs.h tsm_type.h tsm_args.h

How can I adjust my depend rule to accomplish this?

Best regards,
Mark

Hko · 03-06-2009, 11:24 AM

This link provides different approach about this subject (GNU-make specific though):

http://www.gnu.org/software/make/man...-Prerequisites