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Old 04-08-2005, 08:05 PM   #1
BorisMcHack
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Registered: May 2004
Location: uk
Distribution: debian sarge
Posts: 65

Rep: Reputation: 15
make, subdirs, and patsubst


I am trying to use pattern substitution and wildcards to modifiy a Makefile which will compile all src/*.cc files into src/*.o files and then link into the main program.

Unfortunately, I can only find two unsatisfactory sollutions. The first places the object files in the main directory (ie not in src) and then can't find them when it comes to linking. The second places the object files in src, but disregards $(CFLAGS).

Here is the relevant portion of my Makefile:

SRC := $(wildcard src/*.cc)
OBJS := $(SRC:.cc=.o)
HEADERS := $(wildcard include/*.h)

$(PROG): $(OBJS)
# @echo OBJS are $(OBJS)
$(CC) $(CFLAGS) $(OBJS) -o $(PROG)

%.o : %.cc $(HEADERS)
# @echo OBJS are $(OBJS)
$(CC) $(CFLAGS) -c $<

main.o: main.c $(HEADERS)

clean:
rm -f $(PROG) $(OBJS)

BTW: This is the version which places the objs in the main dir. if I change %.o : %.c $(HEADERS) to src/%.o : %.c $(HEADERS) then the other result occurs.

The commented out echos show that atleast the pattern substitution works and that the src/ prefix is there.

I've no clue as to why then that the object files are not placed where I want them to be.

..
BorisMcHack.
 
Old 04-09-2005, 09:41 AM   #2
BorisMcHack
Member
 
Registered: May 2004
Location: uk
Distribution: debian sarge
Posts: 65

Original Poster
Rep: Reputation: 15
The solution was to change
$(CC) $(CFLAGS) -c $<

to
$(CC) $(CFLAGS) -c $< -o $@


I had been confused by the $< thingy, thinking it was magic of some kind. But it's just a variable with the first pre-requisite, ie the each of the source files, and once I knew that, there had to be an equivalant variable for the target...
 
  


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