I don't know if this is possible, but I want to list all my .C files and then be able to use the list to make my program. I have this:

So I'd like to type "make" and have it make each one of the object files, then the program, but instead of evaluating the variables one at a time, it evaluates all of them at once. Is there a way to make it evaluate the variables one at a time (deliniatd by spaces)? Or is there some other way I can automate the make - so that I can just change the file list and have everything just work?

In other words, how would I make the green stuff evaluate one at a time, but everything else evaluate the entire string?

Thanks

I'm no Makefile expert by any means, but perhaps some kind of rule like the following would do it:

.C.o:
$(CXX) -c $< -o $@

Basically just telling make how to create an object file out of a C source file. Not too sure about the syntax...

try something like:
=======================
TARGETS = $(CFILES:.c=)

include include.mk

${TARGETS}:

include.mk:
ls *.c | xargs echo CFILES = > include.mk

heeeyy! that's pretty slick. I didn't know about "xargs" - looks like that's exactly what I was looking for.

Thanks!

I worked out how to do it properly.
this will automagically find
c files and include the header file dependencies
too. ( a bit cleverer than my previous e.g but
still short and sweet!)

They must be simple single source files though
i.e. each with it's own main() and not linked together.

Assuming you have "makedepend" also.

the standard rule is if you do
"make target" it will assume a "target.c" file and cc it.
You don't even need a make file!

like "make func"

will
cc -c func.c -o func.o
cc func.o -o func




# billy billingham
# Thu Mar 11 22:21:13 GMT 2004
#
# ---------------------------------
# Standard makefile for standalone
# C files (not multifile projects)
# e.g. makes 'func.c' with:
#
# cc -c func.c -o func.o
# cc func.o -o func
#
# end up with 'func'
#
#
# using the built-in rules for
# simple single source programs
#
# recursive call to make, first
# call to create the include'd files
# make cannot find the includes so makes them
# before it does the all: target
# ---------------------------------

INCLUDEFILE=files.mk # contains CFILES=
DEPENDFILE=depend.mk # output of makedepend to add the .h deps
TARGETS=$(CFILES:.c=) # remove .c to make the program name

all:
@echo recursive make
$(MAKE) $(TARGETS)
rm $(DEPENDFILE) $(INCLUDEFILE) # remade next time

$(DEPENDFILE):
touch $@
makedepend -f $@ *.c

$(INCLUDEFILE):
echo CFILES= *.c > $@

clean:
-rm *.o

include $(INCLUDEFILE)
include $(DEPENDFILE)