Hi,
I have an Altera DE1 board (
http://www.terasic.com.tw/cgi-bin/pa...oryNo=39&No=83 )
On it there is a flash chip that is 4MB according to the manual. I tryed looking at the numbers of the chip and googling it but got no response back on how to use this memory.
The mapping of pins are as follows
// bidirectional data
inout [7 : 0] FL_DQ;
// address
output [21 : 0] FL_ADDR;
// write enable, output enable, reset enabled
output FL_WE_N, FL_OE_N, FL_RST_N;
This is similar to the sram chip onboard. The only difference is the FL_RST_N, and there is no chip select pin. I adapted the verilog code to this but no luck in reading/writing successfully.
Code:
module flashMemoryctl(
clk,
cs, // request signal
addr, // address
we, // do a write?
setData, // data to write
outData, // data read
ready, // please read now
FL_DQ,
FL_ADDR,
FL_WE_N,
FL_OE_N,
FL_RST_N,
res // reset state machine active low
);
// flash parts
inout [7 : 0] FL_DQ;
output [21 : 0] FL_ADDR;
output FL_WE_N, FL_OE_N, FL_RST_N;
//assign FL_RST_N = res;
// host parts
input clk;
input cs;
input [21: 0] addr;
input we;
input [8 : 0] setData;
output [8 : 0] outData;
output ready;
input res;
wire [8 : 0] sramDina;
wire [8 : 0] sramDout;
wire done;
assign FL_ADDR = addr;
assign FL_OE_N = we? 1'b1 : 1'b0;
assign sramDout = we? 8'bz : FL_DQ ;
assign sramDina = we? setData : 8'bz;
assign FL_DQ = sramDina;
assign FL_RST_N = res;
srwFlash(clk, cs, res, we, FL_WE_N, done);
assign ready = done ;
assign outData = sramDout;
endmodule
module srwFlash(clk, r, res, w, we, now, ss);
input clk, r; // clock / read
input res; // reset
input w; // write?
output we, now;
output [4 : 0] ss; // output of state
wire [15 :0] st, nst; // current + next state
assign ss = st[4 : 0];
memory16(clk, 1'b1, nst, st);
// waiting for button press (r = 1)
assign nst[0] = ((~r & st[0]) | (~r & st[3])) | ~res;
// CS=1
assign nst[1] = res & ((r&st[0]));
// we = 0
assign nst[2] = (st[1]) & res;
// cs - 0 waiting for button release
assign nst[3] = ( (st[3] & r) | st[2]) & res;
//assign rs = ~st[1];
assign we = ~( (st[2] | st[3] ) & w);
// memory is ready to be read
assign now = st[3] | st[2];
endmodule
