exporting makefile variables to $(shell) environment

ta0kira · 05-12-2010, 01:01 PM

I'm aware that one can export make variables to other makefiles; however, how does one export them to the environment of $(shell)? Take the example below:

Code:

export TEST
VARIABLE=$(shell echo $$TEST)
.PHONY: all
all:
	#$(VARIABLE)

In this example, I might call make TEST=test. The goal is for $TEST to be available to the environment of the shell escape. This is because I need its value in a script which is called. For example:

Code:

VARIABLE=$(shell i-need-TEST.sh)

My current solution is the following:

Code:

VARIABLE=$(shell export TEST="$(TEST)"; i-need-TEST.sh)

but this only works if I know all if the variables needed at that point (as opposed to being able to export variables in included makefiles.) Is there an easy solution? Thanks.
Kevin Barry

ntubski · 05-12-2010, 11:05 PM

Environment:

Quote:

When make runs a command script, variables defined in the makefile are placed into the environment of that command. This allows you to pass values to sub-make invocations (see Recursive Use of make). By default, only variables that came from the environment or the command line are passed to recursive invocations. You can use the export directive to pass other variables. See Communicating Variables to a Sub-make, for full details.

Do you need to use the shell function? It seems that the variables aren't exported to its environment.

Code:

~/tmp$ cat v.mk
export TEST
VARIABLE=echo $$TEST
.PHONY: all
all:
        $(VARIABLE)
~/tmp$ make -f v.mk TEST=test
echo $TEST
test

ta0kira · 05-13-2010, 08:20 AM

You're right that the target environment is taken from the makefile; however, I need shell because the targets are taken from a script, and that script determines the targets conditionally, based on the environment. For example:

Code:

#!/bin/bash
#(targets.sh)
eval echo target$SUFFIX.txt

Code:

#makefile

export SUFFIX
TARGETS1=$(shell ./targets.sh)
TARGETS2=$(shell export SUFFIX="$(SUFFIX)"; ./targets.sh)

.PHONY: all TARGETS1 TARGETS2
all: $(TARGETS1) $(TARGETS2)

$(TARGETS1):
	echo TARGET1: $@

$(TARGETS2):
	echo TARGET2: $@

Code:

> make SUFFIX='{-default,-debug}'

Output:

Code:

echo TARGET1: target.txt
TARGET1: target.txt
echo TARGET2: target-default.txt
TARGET2: target-default.txt
echo TARGET2: target-debug.txt
TARGET2: target-debug.txt

Part of the point is that the script being called is also used outside of make; therefore, the script can't be integrated into the makefile itself.
Kevin Barry

ntubski · 05-13-2010, 11:21 AM

It's possible to hack something with .VARIABLES:

Code:

#MAKFILE

# get only the variables with plain names
MAKE_ENV := $(shell echo '$(.VARIABLES)' | awk -v RS=' ' '/^[a-zA-Z0-9]+$$/')
SHELL_EXPORT := $(foreach v,$(MAKE_ENV),$(v)='$($(v))')

export SUFFIX
TARGETS1:=$(shell ./targets.sh)
TARGETS2:=$(shell $(SHELL_EXPORT) ./targets.sh)

.PHONY: all $(TARGETS1) $(TARGETS2)
all: $(TARGETS1) $(TARGETS2)

$(TARGETS1):
	echo TARGET1: $@

$(TARGETS2):
	echo TARGET2: $@

ta0kira · 05-14-2010, 12:45 AM

Thanks, that looks like what I need.
Kevin Barry