thanks all for the reply..
i will make my question more specific....
say for eg: there are 3 .c files (all .c files in the same directory and the Makefile also in the same directory.)
a.c
Code:
#include<stdio.h>
void hello(void);
int main()
{
printf(" hello how are u \n");
hello();
return 0;
}
b.c
Code:
void hello2(void);
void hello(void)
{
printf(" hello how are u 111\n");
hello2();
}
c.c
Code:
void hello2(void)
{
printf(" hello how are u 222\n");
}
and my Makefile is like this..
Code:
RM = /bin/rm -f
PROG = prog
objects := $(patsubst %.c,%.o,$(wildcard *.c))
executablename : $(objects)
gcc -o executablename $(objects)
@echo "hello how are u"
clean:
$(RM) $(PROG) $(objects)
with this make file it will generate an executable named executablename
and if we run ./executablename output is the print statements of all the 3 .c files..
now whats my question is
if say
a.c
Code:
#include<stdio.h>
void hello(void);
int main()
{
printf(" hello how are u \n");
return 0;
}
b.c
Code:
int main()
{
printf(" hello how are u 111\n");
return 0;
}
c.c
Code:
int main()
{
printf(" hello how are u 222\n");
return 0;
}
in this context CAN I WRITE A Makefile (may be with 3 executables,i dunno exactly)???
does that have any sense ???
and if yes how ??
Quote:
|
Originally Posted by wjevans_7d1@yahoo.co
all: alpha beta gamma
alpha: alpha.c
beta: beta.c
gamma: gamma.c
|
sorry i didnt get ???
thanks again....
