basic linking and makefile question

blackzone · 07-20-2006, 07:41 AM

3 file, main calls a function which calls another function.

How do I do the makefile?

main.c:

Code:

#include "dd.h"

int main()
{
  function1();
}

a.c:

Code:

#include "dd.h"

void function1()
{
  function2();
}

b.c:

Code:

#include "dd.h"

void function2()
{
  printf("function2");
}

dd.h:

Code:

void function1(void);
void function2(void);

blackzone · 07-20-2006, 07:46 AM

I dont' know how to do linking. This is my makefile which dont' work.

Code:

main: a.o dd.h
        gcc a.o -o main
a.o: b.o dd.h
        gcc -L b.o -c a.c
b.o: b.c dd.h
        gcc -c b.c

The error is:

Code:

gcc a.o -o main
/usr/lib/gcc/i386-redhat-linux/4.1.0/../../../crt1.o: In function `_start': undefined reference to `main'
a.o: In function `function1':a.c:(.text+0x7): undefined reference to `function2'
collect2: ld returned 1 exit status
make: *** [main] Error 1

bigearsbilly · 07-20-2006, 07:47 AM

try this:

Code:

TARGET=dummy_name
# ---------------------------------
# Standard makefile template
# just specify the target name above
# and the make file should sort it
# all out (hopefully)
# ---------------------------------

INCLUDEFILE = include.mk


# this should appear above the 'include' directive below
# calls for the target and then the cleanup
# =========================================
all: ${TARGET} cleanup 


-include ${INCLUDEFILE}

# ${INCLUDEFILE} should not exist when it's included.
# As it does not exist it is treated as a target.
# Therefore it is created anew each time,
# by the appropriate rule, below
# Which finds .c and .h files and calls makedepend for them
# =========================================================

${INCLUDEFILE}:
 @echo "### creating ${INCLUDEFILE}"
 @echo "### creating ${INCLUDEFILE}" > ${INCLUDEFILE}
 -@ echo  *.c|xargs echo SRCFILES = >> ${INCLUDEFILE}
 -@ echo  *.h|xargs echo HFILES = >> ${INCLUDEFILE}
 @  makedepend  -f${INCLUDEFILE} *.c


# (SRCFILES defined in INCLUDEFILE)
# =================================
OBJFILES = ${SRCFILES:.c=.o}


# this is the working target
# ==========================

${TARGET}: ${OBJFILES} 
 ${CC} -o $@ ${OBJFILES}

help:print_help cleanup

print_help:
 echo  OBJFILES = ${OBJFILES}
 echo  SRCFILES = ${SRCFILES}
 cat ${INCLUDEFILE}
 

clean:cleanup
 -@ rm -f  *.o 

# we need to delete the INCLUDEFILE otherwise
# new source and header files won't be picked up
# next time
# =========
cleanup:
 @echo "### deleting ${INCLUDEFILE}"
 -@ rm -f  ${INCLUDEFILE}

osor · 07-20-2006, 12:11 PM

Howabout this (somewhat less complicated than bigears'):

Code:

main: main.o a.o b.o
        gcc main.o a.o b.o -o main
main.o: main.c dd.h
        gcc -c main.c -o main
a.o: a.c dd.h
        gcc -c a.c
b.o: b.c dd.h
        gcc -c b.c

Or even

Code:

main: a.c b.c main.c dd.h
        gcc main.c a.c b.c -o main