This is my makefile(test.mak):


CC = gcc
INCDIR = ../file1/inc -I ../file2/inc
C_COMPILE_CONTROL = -g
EXEDIR = ../exe/
EXENAME = test
EXEFILE = $(EXEDIR)$(EXENAME)
OBJDIR = ../obj





#------------------------------LINKER---------------------------------#
#It just creates an executable file final.out in dir EXEDIR
#The next line can be commented.

all:$(EXEFILE)
$(EXEFILE):$(OBJDIR)/test.o \
$(OBJDIR)/try.o

$(CC) $^ -o $@ -I$(INCDIR) $(C_COMPILE_CONTROL)




#------------------------COMPILER/ASSEMBLER-----------------------------#
$(OBJDIR)/test.o:../file1/test.c \
../file1/inc/test.h \
../file1/inc/test1.h \
../file1/inc/test2.h

$(CC) -c ../file1/test.c -o $@ -I$(INCDIR) $(C_COMPILE_CONTROL)

#NOTE:$@ = try.o,$^=try.c try.h,HERE can NOT use $^ to replace try.c

$(OBJDIR)/try.o:../file2/try.c \
../file2/inc/try.h
$(CC) -c ../file2/try.c -o $@ -I$(INCDIR) $(C_COMPILE_CONTROL);ls



clean:
rm -rf $(OBJDIR)/*.o


But after I make -f test.mak,*.o are never deleted.that is ,rm -rf $(OBJDIR)/*.o does not work.
So my question is :why?
Thanks.

that's a mighty strange makefile you have here partner.

did you try 'make -f test.mak clean'

default dependency is the first so 'make -f test.mak' is the same as 'make -f test.mak all'

If you want to clean up then build 'make -f test.mak clean all'

I would remove the -r. don't use 'rm -r' unless necessary.

Indent you commands after the target with tabs. I believe you must use tabs and not spaces

eg.
all:$(EXEFILE)
$(EXEFILE):$(OBJDIR)/test.o \
$(OBJDIR)/try.o


For simplicity to can add a rebuild target..

rebuild: clean all

You can change your CC macro to...
CC='gcc -g -c'
and thus clean up your makefile a little

Why are you header files dependencies? You usually don't have to do that unless the make process creates/deletes them.

make -f test.mak clean works.

But i still have another question:
Why cannot *.o be automaticlly deleted after make -f test.mak?

Thank you very much for advice!

because 'make -f test.mak' defaults to 'make -f test.mak <first target in test.mak>'

ie. make command simply executes the first target it finds, in your case that's the all target. If you want 'make -f test.mak' to clean you would have to have the 'clean' target as the first target. but then your all target would not be executed unless you do a 'make -f test.mak all'

The solution would be to add a new target, maybe 'cleanbuild' or something.

cleanbuild: all clean

cleanbuild specifies that all and clean are dependencies and have to be built first. And have cleanbuild as the first target. I don't know why you'd want this though. One of the best things about make is that it allows you to rebuild your project without having to build *every* intermediate file.

You can save yourself typing the 'make -f test.mak' by renaming test.mak to 'Makefile'. make looks for the Makefile file as the default makefile. then you can do 'make clean all', and that would also accomplish what you want.