a strange make rule
 

Hello everyone,


Here is a sample make file.

SRC=foo.c
PROC=$(SRC:%.c=%.o)
TARGET=$(PROC:%.o=$(TARGET_DIR)/%.o)

I know the first two lines mean compile *.c defined in SRC to *.o. But what does the 3rd line mean? Convert *.o generated by PROC to *.o? I am confused that why convert *.o to *.o itself?


thanks in advance,
George

Note the "$(TARGET_DIR)". Many build systems want the object files in a seperate directory because then the object files aren't cluttering up the src directory. It is easier to work in the source when you don't have object files around. "make clean" is really simple too.

Thank you tuxdev,


I have also made some tests on this case. I think in my case, TARGET macro simply prefix $(TARGET_DIR) to each string items in PROC macro. Am I correct?


regards,
George

That is what I think it does as well. I'm not entirely certain about the make-foo, but it makes sense. I have yet to find decent online docs with an explanation of all the neat make features nobody knows about.