Probably an easy one for those in the know, but I've let myself get behind on Makefile theory...
Code:
# $Id: Makefile,v 1.2 2005/02/13 14:23:33 markzero Exp $
CC = cc
CFLAGS = -pipe -O -W -Wall -pedantic -ansi
RM = /bin/rm -f
all: SWp_API_logerr SWp_new SWp_tsuite_tools SWp_logerr
SWp_API_logerr: $(.TARGET).c $(.TARGET).h
SWp_new: $(.TARGET).c $(.TARGET).h $(.TARGET).r SWp_API_logerr
SWp_tsuite_tools: $(.TARGET).c $(.TARGET).h
SWp_logerr: $(.TARGET).c $(.TARGET).h
SWp_example_object: $(.TARGET).c $(.TARGET).h SWp_new
.c:
$(CC) $(CFLAGS) -c $(.IMPSRC) -o $(.TARGET).o
clean:
$(RM) *.o *.core
I want to add a new target - 'ExampleObjTest'. It's a single C source file that depends on SWP_new and SWp_example_object and should result in an executable.
What would be the tidiest and most concise way of adding ExampleObjTest given the implicit '.c' target?
Uh, perhaps not the best way to explain it.