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I am using AT91SAM9260 and running Linux 2.6.27 on it. Once i sync the Kernel clock and cmos clock with the reference clock and leave it for 1 day, i see a drift of nearly 8-10 sec. The kernel clock is running faster. How can i correct this?
Have you double checked crystal speeds?
One way out of this messing is to use a 32.768khz crystal for your timer, if the chip allows it.
Last circuit I put out I had a spare leg somewhere and I toggled it every 0.1 secs or suchlike. Then I could scope it to deal with those problems.
Have you double checked crystal speeds?
One way out of this messing is to use a 32.768khz crystal for your timer, if the chip allows it.
Last circuit I put out I had a spare leg somewhere and I toggled it every 0.1 secs or suchlike. Then I could scope it to deal with those problems.
I am using following
32khz:*** Epson Toyocom* MC-306.32768-A0:ROHS, Fox FSRLF327
18.432MHz: Abracon ABM3B-18.432D2W** -40C to 85C* +/-20ppm tolerance and +/-25ppm stability
This goes away from software entirely. There's 86,400 seconds in a day. You are complaining about 10 of them, which is an inaccuracy of ~0.0014%
Your options are: use an ntp client & server, which fixes this in software, or slightly tweak whatever parallel capacitance you have on the crystal. Alternatively, buy a better @$£! crystal - or simply another one. Ever wonder why cheap watches don't keep time?
This goes away from software entirely. There's 86,400 seconds in a day. You are complaining about 10 of them, which is an inaccuracy of ~0.0014%
Your options are: use an ntp client & server, which fixes this in software, or slightly tweak whatever parallel capacitance you have on the crystal. Alternatively, buy a better @$£! crystal - or simply another one. Ever wonder why cheap watches don't keep time?
I am using 18pF 5% 50V capacitor. As per the crystal oscillator it C load shall have typical value of 19pF. Is that differnece going to effect in anyway?
I am not getting your point "how the capacitance value can affect the system clock drift"?
RC time constant? Usually the clock is a chip with a resonant frequency but it might be possible to be changed slightly.
Without a time standard it would be difficult to ever keep it in time. I agree that a ntp check is the best choice.
I agree with you that ntp is the best choice and it does work for our board. But our board is not always connected to the network, so that will create a problem. Since, we are always seeing a constant drift of 8sec/day, Is there any workaround in kernel so that we can correct the drift,say, after every 1 hour or so.
I am using 18pF 5% 50V capacitor. As per the crystal oscillator it C load shall have typical value of 19pF. Is that differnece going to effect in anyway?
I am not getting your point "how the capacitance value can affect the system clock drift"?
Is it adjustable? If so, my suggestion was to tweak it. Within limits, the larger the capacitance, the slower your xtal will run.
Last edited by business_kid; 07-09-2010 at 02:44 AM.
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