[SOLVED] need of makefile info ? how the linux make file is different from simple c makefile ?

rpittala · 05-07-2012, 12:48 PM

Hi Folks,
I am in need of some Makefile information. Actually, I am in little bit confusion after looking at LINUX Makefile and the C application type Makefile. what is the difference between the above Make files and how many types of Makefiles are there?

Having knowledge on application side Makefile`s and looking for application side Makefiles documents as well.

Looking forward to know useful info and some useful URL`s to study

knudfl · 05-07-2012, 05:37 PM

Not quite clear what you mean with :
"LINUX Makefile and the C application type Makefile".

Linux is the kernel, and all kernel files are c programs.
There is a "standard" Makefile for a single kernel module :

Code:

obj-m    := hello.o

KDIR    := /lib/modules/$(shell uname -r)/build
PWD    := $(shell pwd)

default:
	$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules

... And then some links for all other Makefiles, etc.
http://www.gnu.org/software/autoconf/manual/index.html
http://www.gnu.org/software/autoconf/
http://www.gnu.org/software/automake/
http://sourceware.org/autobook/

http://www.freesoftwaremagazine.com/..._gnu_autotools
http://www.freesoftwaremagazine.com/...with_autotools
http://www.freesoftwaremagazine.com/..._with_autoconf

http://www.developingprogrammers.com...ools-tutorial/

http://www.wlug.org.nz/MakefileHowto
http://www.eng.hawaii.edu/Tutor/Make/
http://www.linuxplanet.com/linuxplan...orials/7093/1/
http://www.gnu.org/software/make/manual/make.html
http://www.student.cs.uwaterloo.ca/~isg/res/unix/make/

rpittala · 05-07-2012, 09:04 PM

Yes, I was talking about Linux makefile(kernel modules) as per the above MAkefile code and at the same time the below Makefile code

Code:

CC = gcc
CFLAGS = -Wall -g
OBJECTS = app.o
out.exe :$(OBJECTS)
       $(CC) $(CFLAGS) $(OBJECTS) -o out.exe
app.o : header.h app.c
       $(CC) $(CFLAGS) -c app.c