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Old 03-03-2012, 09:07 PM   #1
Registered: Jul 2005
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Makefile question

I'm just reading trying to get a further understanding of building and installing kernel modules. I'm looking at some Makefile examples and notice the pattern that they seem to follow, For example:
obj-m := hello.o
KDIR := /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
I'm not much of a scripting guy but I'm confused about the KDIR target when it uses variable $(shell uname -r) as the target. Shouldn't it be just $(uname -r), command substitution does not work for me with shell included.

[delslige@Fedora-VM1 modules]$ echo $(uname -r)
[delslige@Fedora-VM1 modules]$ echo $(shell uname -r)
-bash: shell: command not found
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Old 03-03-2012, 09:13 PM   #2
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A Makefile is not a shell script. A Makefile has its own variable assignment and substitution syntax.

What is confusing is that the Makefile syntax uses some very similar syntax to bash shell scripts. So it's easy to get them confused.

In the Makefile, you must use $(shell [command]) to tell the make command to issue a shell command and substitute the output. That's just how it works. See the GNU Make Manual for all the gory details.

And as a side note, in your example, neither KDIR nor $(shell ...) is a "target." KDIR is a Makefile variable and $(shell ...) is a function call. A target is always defined as "<target name> : <target dependencies>"

Last edited by Dark_Helmet; 03-03-2012 at 09:15 PM.
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Old 03-03-2012, 09:16 PM   #3
Registered: Jul 2005
Posts: 51

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I have a lot to learn. Thanks for clearing that up.


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