Ok I'm really newb to this,

I wrote a program, say robot.cc, and i want to write a makefile for it, so that when i type

robot [filename]

where filename is an input file, it will compile the robot.cc and take in the input file with name "filename", and if filename is not present, then just run

./a.out instead of ./a.out filename

i know it looks something like

robot $X:
g++ robot.cc
./a.out $X

but doesnt seem to work

Thanks in advance.

Why do you want to force a recompile of the robot.cc
on every run in the first place?


Cheers,
Tink

not everytime, just compile once, the next time robot is called, assume no changes in *.cc, it will be robot instead of ./a.out

When you type robot, how do you want the Makefile to be used ?
Usually a Makefile is processed by the make command.

Or is it "make robot" what you meant ?

I guess we more experienced folks are just a bit confused about what you are trying to do.

A makefile is used by the "make" command to compile source code into an executable program. (Yeah, it *can* do more, but that's its basic intent. ) So you type

$ make robot

and the instructions in the makefile will take robot.cc and produce an executable program, presumably named "robot". Then, you run "robot" by typing

$ robot [filename]

and "robot" will do whatever it's supposed to do with "filename".

If this isn't what you are trying to do, we need a little more clarification.