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Old 07-14-2016, 11:10 AM   #1
GreyBeard
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tsc: Marking TSC unstable due to check_tsc_sync_source failed


Hi,

I just noticed a boot-time error message which I have not noticed before, so I went looking to find out what it was. I run Slackware 14.2, but I think this is not a Slackware issue. Here is the message from /var/log/messages:

kernel: [ 0.050000] tsc: Marking TSC unstable due to check_tsc_sync_source failed

I had no idea what TSC is but I found one message which implied that it had something to do with system clocking or timing, so I narrowed my search. Found the answer in Wikipedia at https://en.wikipedia.org/wiki/Time_Stamp_Counter#Use which explains quite plainly why the TSC is marked as unstable:

--------------------------------------------------------
The Time Stamp Counter was once an excellent high-resolution, low-overhead way for a program to get CPU timing information. With the advent of multi-core/hyper-threaded CPUs, systems with multiple CPUs, and hibernating operating systems, the TSC cannot be relied upon to provide accurate results unless great care is taken to correct the possible flaws: rate of tick and whether all cores (processors) have identical values in their time-keeping registers. There is no promise that the timestamp counters of multiple CPUs on a single motherboard will be synchronized. Therefore, a program can get reliable results only by limiting itself to run on one specific CPU. Even then, the CPU speed may change because of power-saving measures taken by the OS or BIOS, or the system may be hibernated and later resumed, resetting the TSC. In those latter cases, to stay relevant, the program must re-calibrate the counter periodically.
--------------------------------------------------------

Since I have a 4 processor CPU chip in my machine it is quite clear that the TSC should be marked as unstable. This message is not an error but a feature.
 
Old 07-16-2016, 01:12 PM   #2
seasons
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Was there a question in here? Yeah, it's a common message (and not specific to Slack).

Quote:
Since I have a 4 processor CPU chip in my machine it is quite clear that the TSC should be marked as unstable.
Hmm. I have a 3 core (Phenom II X3 720) chip and it switches to tsc early in boot process after initally selectin hpet. IIRC, I once played with forcing clocksource=hpet to see if it made any sort of perceivable difference. It didn't.

Code:
$ cat /sys/devices/system/clocksource/clocksource0/available_clocksource
tsc hpet acpi_pm 
$ cat /sys/devices/system/clocksource/clocksource0/current_clocksource 
tsc

$ dmesg | grep -i clocksource
[    0.000000] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 6370452778343963 ns
[    0.000000] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 133484873504 ns
[    0.365982] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 6370867519511994 ns
[    0.439907] clocksource: Switched to clocksource hpet
[    0.447372] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns
[    2.769844] tsc: Refined TSC clocksource calibration: 2800.107 MHz
[    2.769848] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x285ca5e6db0, max_idle_ns: 440795312341 ns
[    3.769861] clocksource: Switched to clocksource tsc
 
  


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