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Old 06-02-2009, 09:30 AM   #1
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Registered: Jan 2009
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pgprot_noncached when mapping io memory to user space

Dear experts,

I am writing a driver for a PCIe board. This board is configurable through IO memory regions (bars 0 & 1). These bars are exposed to the user space program thanks to the following driver code:

static int BLA_mmap(struct file *pFile, struct vm_area_struct *pVma)
   /* -- nResourceStart is the value returned by pci_resource_start -- */

   pVma->vm_page_prot = pgprot_noncached(pVma->vm_page_prot);
   pVma->vm_flags |= VM_RESERVED | VM_IO;

   return remap_pfn_range(pVma, pVma->vm_start, nResourceStart >> PAGE_SHIFT, pVma->vm_end - pVma->vm_start, pVma->vm_page_prot);
Thus, I can access these regions from user space with a simple pointer (after calling mmap):

pBar[0] = 2;
bla = pBar[1];
My question is about instructions caching. Although pgprot_noncached is used, I wonder if the operations performed through this pointer will be made exactly in the specified order or if any kind of reordering is likely to be performed by the CPU. If reoerdering is performed, is there a standard way to prevent this from happening?

I read Documentation/memory-barriers.txt but I did not find the answer ...

Any help appreciated !

Best regards,

Old 06-20-2011, 01:08 PM   #2
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Registered: Jun 2011
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Hello! i had the same problem - even with nocache prot flag i noticed some latency in write/read - when user-space application writes to mmaped area, immediately after that driver did not see the new data - only after some delay data become coherent. Have you found out how to solve this problem? - i'm rather curious that application is seemed to work with "copy" of RAM-page, not directly with mapped area.


cache, io, remapping

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