Hello Experts,

I'm writing driver for pcie xilinx fpga. The fpga hardware team has not given me any interrupt status register, interrupt enable register. They just said to set the bit 9 in the device control register which would enable the interrupt(for read or write completion). Is this sufficient to handle the interrupts? When I register the interrupt with a shared flag, my handler gets called even when the bit 9 is reset, how do i make sure if the appropriate interrupt is being received? How do i control it? Do i need to request the fpga hardware to add any extra registers?

please help.

Thanks a ton.

The interrupt needs to come up in a disabled state and be enabled by your driver. Otherwise it could trigger before your driver is loaded. If you want to be able to unload your driver, then you also need a way to disable the interrupt before you do.

Thanks for the reply. But does this answer my queries?

Appreciate your help.

Thanks.

Maybe not.

You only need status if there is not some other way to tell if the chip interrupted - like a memory buffer being written, for example. You don't give much detail about operation.

If interrupts are chained, then you need some way to tell if the int is for you.
You also need a way to clear it if responding twice to one interrupt is a problem.