Hi all,

I am trying to implement a simple PCI driver for my sound card. But I think that I face a strange situation here. I will try to explain what I do and will ask my questions meanwhile:

As far as I understood each PCI device has IO PORTS and IO MEMORY assigned to it. IS THIS TRUE?


Because what I see in my case is this:

- I succeed reserving IO PORTS.
Code:
ioport = pci_resource_start(dev, 0);
ioport_len = pci_resource_len(dev, 0);
The info for these ports is ioport = 0xd100 and ioport_len = 0x0100
request_region(ioport, ioport_len, name); ===>>> OK

- I fail to reserve IO MEMORY.
Code:
iomem = pci_resource_start(dev, 1);
iomem_len = pci_resource_len(dev, 1);
The info for the io memory is iomem = 0xd200 and iomem_len = 0x0040
request_region(iomem, iomem_len, name); ===>>> FAIL!


So I don't see my driver in /proc/iomem.

I see my driver twice(???) in /proc/ioports:
d100-d1ff : pci_drv_temp
d200-d23f : pci_drv_temp


So it seems that pci_resource_start(dev, 1) returns only addresses in the io_port area. What could cause this?

Could this be caused by the device itself?
I checked the original device driver with lspci -v and it also does not list any iomemory(only ioports). Which makes me that indeed the device does not have iomemory. Could this be the case?



I am not sure if I have explained myself well enough. Please let me know if this is the case? I can give a better shot.
Thank you.

References to devices can be made with regular memory cycles (memory space) or they can be done with I/O cycles (I/O space). It is up to how the hardware is designed as to which type of bus cycles it responds to: IO, memory or both. When the device is first initialized it uses a 3rd space, PCI configuration space, to set up the memory and I/O regions that will be used by the driver.

In your case, if only IO space is supported, you must access the device via I/O space.

Smallpond thanks for the answer.

Indeed this was my conclusion as well. I came up with it after checking another sound device, which had both IO ports and IO memory.

So yes it depends on the device chip how it can be accessed.