Actually, that's not quite right ... I think.
"The cache" refers to the on-chip cache lines that are part of the virtual-memory subsystem, used to avoid repeated reference to page and segment tables (which, of course, would triple the number of memory accesses and thereby bring the whole thing to a screeching plod). When you do something that affects segmentation, e.g. discarding stuff, changing page-table entries and so on, you must invalidate those parts of the CPU caches. (And all CPUs must do so.) There are established procedures and macros etc. for this. They must be followed precisely, so that your code is 100%-reliable on all processors, in actual conditions under heavy loads.
I don't momentarily recall if the CPU will attempt to cache content, but it would not surprise me. Suffice it to say that, anywhere a cache could be present, you must correctly advise the hardware when to invalidate it, and you must do so in the most specific (hence, least intrusive) way possible.
Last edited by sundialsvcs; 11-20-2012 at 08:31 AM.