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Old 08-14-2012, 01:41 AM   #1
rsathyadav
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Question Page Sizes for Different Processors


Hello,
Can anyone tell me how the default page size is chosen as 4kb?
All pages i referred says that its fixed by the MMU.
Basically, i want to know why the page size is fixed as 4K for 32 bit proc and 8K for 64 bit proc..
How the whole process is carried out by the MMU?

Thank you.
 
Old 08-14-2012, 02:12 AM   #2
jschiwal
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The CPU accesses virtual memory. 2 tables of pointers are used to reach the physical memory. This allows programs to be written using the same memory addresses, and allows the computer to have more total memory. If you use the PAE extension, the page size is 32k .
 
Old 08-14-2012, 02:37 AM   #3
SIG_SEGV
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Paging is implemented by breaking up the memory address into a page number and offset number. It is most efficient to break the address into X page bits and Y offset bits, rather than perform arithmetic on the address to calculate the page number and offset.

And the width of segmentation registers (MMU registers) depends on the processor... if MMU reg is of 32bits (for 32 bit processors) then page number is 20bits wide and remaining 12 bits (2^12) represent 4096 bytes .so a total of 4kb/page and 20 bits inturn represent 1048576 pages, implying (1048576 * 4096 = 4GB of total memory).Because each bit position represents a power of 2, splitting an address between bits results in a page size that is a power of 2 always.
 
Old 08-14-2012, 02:55 AM   #4
colucix
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Moved: This thread is more suitable in Linux - Hardware and has been moved accordingly to help your thread/question get the exposure it deserves.
 
Old 08-14-2012, 03:51 AM   #5
rsathyadav
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My qn was why is the page number 20 bits and why is offset 12 bits.
If i am not wrong ur explanation states exact reverse of what i am asking.
2 raised 12 makes 4kb, hence 12 bits is fine.

My qn is why 4KB? How is it selected. What is the math.

Thanks
 
Old 08-14-2012, 09:12 AM   #6
SIG_SEGV
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Well i expected this question... Here i go,
if the offset is too low for example, only 2 bits then, each page would contain only 2^2=4bytes memory locations and since remaining 30 bits represent 2^30 pages addressing capability, there would be 2^30 pages. Now the problem is "your every program (even if its small i.e of 40 bytes) tends to order for large number of pages (40/4=10), by which the MMU cannot manage good speed in physical address translation for the CPU. Same way, if the offset is of large quantity (ex: 30) bits, then each page would have consisted (2^30) bytes, in which case evry single program (even if its of 2byte sized pgm) would taken 2^30 bytes of memory since every time the memory is given to the program in terms of pages. so to overcome the bottlenecks of these two overhead constraints, the engineer's choice was made.
That is 20 bits for pg.no and 12 bits for offset to gain the acceptable efficiency.

Convinced????
 
  


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