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Old 07-13-2020, 06:02 AM   #1
hd_scania
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Registered: Apr 2017
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Issues flashing Coreboot 4.12 on Sony VPCCB17FG


Coreboot flashing system: KDE Plasma on Artix-runit
Code:
hd-scania:[hd_scania]:/home/data/terminal/coreboot/coreboot$ make
/home/data/terminal/coreboot/coreboot/util/crossgcc/xgcc/bin/x86_64-elf-ld.bfd:build/romstage/drivers/elog/boot_count.o: file format not recognized; treating as linker script
/home/data/terminal/coreboot/coreboot/util/crossgcc/xgcc/bin/x86_64-elf-ld.bfd:build/romstage/drivers/elog/boot_count.o:1: syntax error
make: *** [src/arch/x86/Makefile.inc:185: build/cbfs/fallback/romstage.debug] エラー 1
hd-scania:[hd_scania]:/home/data/terminal/coreboot/coreboot$
Code:
hd-scania:[hd_scania]:/home/data/terminal/coreboot/coreboot$ sudo make config
*
* coreboot configuration
*
*
* General setup
*
Local version string (LOCALVERSION) [] (NEW) 4.12
Compiler to use
> 1. GCC (COMPILER_GCC) (NEW)
  2. LLVM/clang (TESTING ONLY - Not currently working) (COMPILER_LLVM_CLANG) (NEW)
choice[1-2?]: 1
Allow building with any toolchain (ANY_TOOLCHAIN) [N/y/?] (NEW) y
Use ccache to speed up (re)compilation (CCACHE) [N/y/?] (NEW) y
Generate flashmap descriptor parser using flex and bison (FMD_GENPARSER) [N/y/?] (NEW) y
Generate SCONFIG & BINCFG parser using flex and bison (UTIL_GENPARSER) [N/y/?] (NEW) y
Use CMOS for configuration values (USE_OPTION_TABLE) [N/y/?] (NEW) y
  Load default configuration values into CMOS on each boot (STATIC_OPTION_TABLE) [N/y/?] (NEW) y
Compress ramstage with LZMA (COMPRESS_RAMSTAGE) [Y/n/?] (NEW) y
Include the coreboot .config file into the ROM image (INCLUDE_CONFIG_FILE) [Y/n/?] (NEW) y
Create a table of timestamps collected during boot (COLLECT_TIMESTAMPS) [Y/n/?] (NEW) n
Allow use of binary-only repository (USE_BLOBS) [Y/n/?] (NEW) y
  Allow AMD blobs repository (with license agreement) (USE_AMD_BLOBS) [N/y/?] (NEW) n
  Allow QC blobs repository (selecting this agrees to the license!) (USE_QC_BLOBS) [N/y/?] (NEW) y
Code coverage support (COVERAGE) [N/y/?] (NEW) y
Undefined behavior sanitizer support (UBSAN) [N/y/?] (NEW) y
Stage Cache for ACPI S3 resume
> 1. Disabled (NO_STAGE_CACHE) (NEW)
  2. CBMEM (CBMEM_STAGE_CACHE) (NEW)
choice[1-2]: 2
Update existing coreboot.rom image (UPDATE_IMAGE) [N/y/?] (NEW) y
Add a bootsplash image (BOOTSPLASH_IMAGE) [N/y/?] (NEW) y
  Bootsplash path and filename (BOOTSPLASH_FILE) [bootsplash.jpg] (NEW) /home/data/lib/Pictures/lelouch.zero.beast.png
Firmware Configuration Probing (FW_CONFIG) [N/y/?] (NEW) y
  Obtain Firmware Configuration value from CBFS (FW_CONFIG_SOURCE_CBFS) [N/y/?] (NEW) y
*
* Mainboard
*
*
* Important: Run 'make distclean' before switching boards
*
Mainboard vendor
  1. 51NB (VENDOR_51NB) (NEW)
  2. ADLINK (VENDOR_ADLINK) (NEW)
  3. AMD (VENDOR_AMD) (NEW)
  4. AOpen (VENDOR_AOPEN) (NEW)
  5. Apple (VENDOR_APPLE) (NEW)
  6. ASROCK (VENDOR_ASROCK) (NEW)
  7. ASUS (VENDOR_ASUS) (NEW)
  8. BAP (VENDOR_BAP) (NEW)
  9. Biostar (VENDOR_BIOSTAR) (NEW)
  10. Cavium (VENDOR_CAVIUM) (NEW)
  11. CompuLab (VENDOR_COMPULAB) (NEW)
  12. Dell Inc. (VENDOR_DELL) (NEW)
  13. ELMEX (VENDOR_ELMEX) (NEW)
> 14. Emulation (VENDOR_EMULATION) (NEW)
  15. Facebook (VENDOR_FACEBOOK) (NEW)
  16. Foxconn (VENDOR_FOXCONN) (NEW)
  17. Getac (VENDOR_GETAC) (NEW)
  18. GIGABYTE (VENDOR_GIGABYTE) (NEW)
  19. GizmoSphere (VENDOR_GIZMOSPHERE) (NEW)
  20. Google (VENDOR_GOOGLE) (NEW)
  21. HP (VENDOR_HP) (NEW)
  22. iBase (VENDOR_IBASE) (NEW)
  23. Intel (VENDOR_INTEL) (NEW)
  24. Jetway (VENDOR_JETWAY) (NEW)
  25. Kontron (VENDOR_KONTRON) (NEW)
  26. Lenovo (VENDOR_LENOVO) (NEW)
  27. Libretrend (VENDOR_LIBRETREND) (NEW)
  28. LiPPERT (VENDOR_LIPPERT) (NEW)
  29. MSI (VENDOR_MSI) (NEW)
  30. Open Compute Project (VENDOR_OCP) (NEW)
  31. OpenCellular (VENDOR_OPENCELLULAR) (NEW)
  32. Packard Bell (VENDOR_PACKARDBELL) (NEW)
  33. PC Engines (VENDOR_PCENGINES) (NEW)
  34. Portwell (VENDOR_PORTWELL) (NEW)
  35. Prodrive (VENDOR_PRODRIVE) (NEW)
  36. Protectli (VENDOR_PROTECTLI) (NEW)
  37. Purism (VENDOR_PURISM) (NEW)
  38. RAZER (VENDOR_RAZER) (NEW)
  39. Roda (VENDOR_RODA) (NEW)
  40. SAMSUNG (VENDOR_SAMSUNG) (NEW)
  41. Sapphire (VENDOR_SAPPHIRE) (NEW)
  42. Scaleway (VENDOR_SCALEWAY) (NEW)
  43. Siemens (VENDOR_SIEMENS) (NEW)
  44. SiFive (VENDOR_SIFIVE) (NEW)
  45. Supermicro (VENDOR_SUPERMICRO) (NEW)
  46. System76 (VENDOR_SYSTEM76) (NEW)
  47. TI (VENDOR_TI) (NEW)
  48. UP (VENDOR_UP) (NEW)
choice[1-48]: 23
Mainboard model
> 1. Apollolake DDR3 RVP1 (BOARD_INTEL_APOLLOLAKE_RVP1) (NEW)
  2. Apollolake LPDDR3 RVP2 (BOARD_INTEL_APOLLOLAKE_RVP2) (NEW)
  3. Basking Ridge CRB (BOARD_INTEL_BASKING_RIDGE) (NEW)
  4. Cannonlake U LPDDR4 RVP (BOARD_INTEL_CANNONLAKE_RVPU) (NEW)
  5. Cannonlake Y LPDDR4 RVP (BOARD_INTEL_CANNONLAKE_RVPY) (NEW)
  6. Cedar Island CRB (BOARD_INTEL_CEDARISLAND_CRB) (NEW)
* Coffeelake RVP
  7. -> Coffeelake U SO-DIMM DDR4 RVP (BOARD_INTEL_COFFEELAKE_RVPU) (NEW)
  8. -> Coffeelake H SO-DIMM DDR4 RVP11 (BOARD_INTEL_COFFEELAKE_RVP11) (NEW)
  9. -> Whiskeylake U DDR4 RVP (BOARD_INTEL_WHISKEYLAKE_RVP) (NEW)
  10. -> Coffeelake S U-DIMM DDR4 RVP8 (BOARD_INTEL_COFFEELAKE_RVP8) (NEW)
  11. -> Cometlake U DDR4 RVP (BOARD_INTEL_COMETLAKE_RVPU) (NEW)
  12. D510MO / D410PT (BOARD_INTEL_D510MO) (NEW)
  13. D945GCLF (BOARD_INTEL_D945GCLF) (NEW)
  14. Intel NUC DCP847SKE (BOARD_INTEL_DCP847SKE) (NEW)
  15. DG41WV (BOARD_INTEL_DG41WV) (NEW)
  16. DG43GT (BOARD_INTEL_DG43GT) (NEW)
  17. Emerald Lake 2 CRB (BOARD_INTEL_EMERALDLAKE2) (NEW)
  18. Galileo (BOARD_INTEL_GALILEO) (NEW)
  19. Glkrvp (BOARD_INTEL_GLKRVP) (NEW)
  20. Harcuvar CRB (BOARD_INTEL_HARCUVAR) (NEW)
  21. Icelake U DDR4/LPDDR4 RVP (BOARD_INTEL_ICELAKE_RVPU) (NEW)
  22. Icelake Y LPDDR4 RVP (BOARD_INTEL_ICELAKE_RVPY) (NEW)
  23. Jasperlake DDR4/LPDDR4 RVP (BOARD_INTEL_JASPERLAKE_RVP) (NEW)
  24. Jasperlake DDR4/LPDDR4 RVP with Chrome EC (BOARD_INTEL_JASPERLAKE_RVP_EXT_EC) (NEW)
  25. Kabylake LPDDR3 RVP3 (BOARD_INTEL_KBLRVP3) (NEW)
  26. Kabylake DDR3L RVP7 (BOARD_INTEL_KBLRVP7) (NEW)
  27. Kabylake DDR4 RVP8 (BOARD_INTEL_KBLRVP8) (NEW)
  28. Kabylake DDR4 RVP11 (BOARD_INTEL_KBLRVP11) (NEW)
  29. Kunimitsu (BOARD_INTEL_KUNIMITSU) (NEW)
  30. Leafhill (BOARD_INTEL_LEAFHILL) (NEW)
  31. Minnow3 (BOARD_INTEL_MINNOW3) (NEW)
  32. Skylake Saddle Brook (BOARD_INTEL_SKLSDLBRK) (NEW)
  33. Strago (BOARD_INTEL_STRAGO) (NEW)
  34. Tigerlake UP3 RVP (BOARD_INTEL_TGLRVP_UP3) (NEW)
  35. Tigerlake UP4 RVP (BOARD_INTEL_TGLRVP_UP4) (NEW)
  36. Whitetip Mountain 2 CRB (BOARD_INTEL_WTM2) (NEW)
choice[1-36]: 0
Mainboard model
> 1. Apollolake DDR3 RVP1 (BOARD_INTEL_APOLLOLAKE_RVP1) (NEW)
  2. Apollolake LPDDR3 RVP2 (BOARD_INTEL_APOLLOLAKE_RVP2) (NEW)
  3. Basking Ridge CRB (BOARD_INTEL_BASKING_RIDGE) (NEW)
  4. Cannonlake U LPDDR4 RVP (BOARD_INTEL_CANNONLAKE_RVPU) (NEW)
  5. Cannonlake Y LPDDR4 RVP (BOARD_INTEL_CANNONLAKE_RVPY) (NEW)
  6. Cedar Island CRB (BOARD_INTEL_CEDARISLAND_CRB) (NEW)
* Coffeelake RVP
  7. -> Coffeelake U SO-DIMM DDR4 RVP (BOARD_INTEL_COFFEELAKE_RVPU) (NEW)
  8. -> Coffeelake H SO-DIMM DDR4 RVP11 (BOARD_INTEL_COFFEELAKE_RVP11) (NEW)
  9. -> Whiskeylake U DDR4 RVP (BOARD_INTEL_WHISKEYLAKE_RVP) (NEW)
  10. -> Coffeelake S U-DIMM DDR4 RVP8 (BOARD_INTEL_COFFEELAKE_RVP8) (NEW)
  11. -> Cometlake U DDR4 RVP (BOARD_INTEL_COMETLAKE_RVPU) (NEW)
  12. D510MO / D410PT (BOARD_INTEL_D510MO) (NEW)
  13. D945GCLF (BOARD_INTEL_D945GCLF) (NEW)
  14. Intel NUC DCP847SKE (BOARD_INTEL_DCP847SKE) (NEW)
  15. DG41WV (BOARD_INTEL_DG41WV) (NEW)
  16. DG43GT (BOARD_INTEL_DG43GT) (NEW)
  17. Emerald Lake 2 CRB (BOARD_INTEL_EMERALDLAKE2) (NEW)
  18. Galileo (BOARD_INTEL_GALILEO) (NEW)
  19. Glkrvp (BOARD_INTEL_GLKRVP) (NEW)
  20. Harcuvar CRB (BOARD_INTEL_HARCUVAR) (NEW)
  21. Icelake U DDR4/LPDDR4 RVP (BOARD_INTEL_ICELAKE_RVPU) (NEW)
  22. Icelake Y LPDDR4 RVP (BOARD_INTEL_ICELAKE_RVPY) (NEW)
  23. Jasperlake DDR4/LPDDR4 RVP (BOARD_INTEL_JASPERLAKE_RVP) (NEW)
  24. Jasperlake DDR4/LPDDR4 RVP with Chrome EC (BOARD_INTEL_JASPERLAKE_RVP_EXT_EC) (NEW)
  25. Kabylake LPDDR3 RVP3 (BOARD_INTEL_KBLRVP3) (NEW)
  26. Kabylake DDR3L RVP7 (BOARD_INTEL_KBLRVP7) (NEW)
  27. Kabylake DDR4 RVP8 (BOARD_INTEL_KBLRVP8) (NEW)
  28. Kabylake DDR4 RVP11 (BOARD_INTEL_KBLRVP11) (NEW)
  29. Kunimitsu (BOARD_INTEL_KUNIMITSU) (NEW)
  30. Leafhill (BOARD_INTEL_LEAFHILL) (NEW)
  31. Minnow3 (BOARD_INTEL_MINNOW3) (NEW)
  32. Skylake Saddle Brook (BOARD_INTEL_SKLSDLBRK) (NEW)
  33. Strago (BOARD_INTEL_STRAGO) (NEW)
  34. Tigerlake UP3 RVP (BOARD_INTEL_TGLRVP_UP3) (NEW)
  35. Tigerlake UP4 RVP (BOARD_INTEL_TGLRVP_UP4) (NEW)
  36. Whitetip Mountain 2 CRB (BOARD_INTEL_WTM2) (NEW)
choice[1-36]: 17
Mainboard vendor name (MAINBOARD_VENDOR) [Intel] (NEW) Sony
ROM chip size
  1. 64 KB (COREBOOT_ROMSIZE_KB_64) (NEW)
  2. 128 KB (COREBOOT_ROMSIZE_KB_128) (NEW)
  3. 256 KB (COREBOOT_ROMSIZE_KB_256) (NEW)
  4. 512 KB (COREBOOT_ROMSIZE_KB_512) (NEW)
  5. 1024 KB (1 MB) (COREBOOT_ROMSIZE_KB_1024) (NEW)
  6. 2048 KB (2 MB) (COREBOOT_ROMSIZE_KB_2048) (NEW)
  7. 4096 KB (4 MB) (COREBOOT_ROMSIZE_KB_4096) (NEW)
  8. 5120 KB (5 MB) (COREBOOT_ROMSIZE_KB_5120) (NEW)
  9. 6144 KB (6 MB) (COREBOOT_ROMSIZE_KB_6144) (NEW)
> 10. 8192 KB (8 MB) (COREBOOT_ROMSIZE_KB_8192) (NEW)
  11. 10240 KB (10 MB) (COREBOOT_ROMSIZE_KB_10240) (NEW)
  12. 12288 KB (12 MB) (COREBOOT_ROMSIZE_KB_12288) (NEW)
  13. 16384 KB (16 MB) (COREBOOT_ROMSIZE_KB_16384) (NEW)
  14. 32768 KB (32 MB) (COREBOOT_ROMSIZE_KB_32768) (NEW)
  15. 65536 KB (64 MB) (COREBOOT_ROMSIZE_KB_65536) (NEW)
choice[1-15?]: 10
System Power State after Failure
> 1. S5 Soft Off (POWER_STATE_OFF_AFTER_FAILURE) (NEW)
  2. S0 Full On (POWER_STATE_ON_AFTER_FAILURE) (NEW)
  3. Keep Previous State (POWER_STATE_PREVIOUS_AFTER_FAILURE) (NEW)
choice[1-3?]: 1
fmap description file in fmd format (FMDFILE) [] (NEW) 
  Size of CBFS filesystem in ROM (CBFS_SIZE) [0x100000] (NEW) 
*
* Chipset
*
*
* SoC
*
*
* CPU
*
Enable VMX for virtualization (ENABLE_VMX) [Y/n] (NEW) y
Set IA32_FEATURE_CONTROL lock bit (SET_IA32_FC_LOCK_BIT) [Y/n/?] (NEW) n
Include CPU microcode in CBFS
> 1. Generate from tree (CPU_MICROCODE_CBFS_DEFAULT_BINS) (NEW)
  2. Include external microcode binary (CPU_MICROCODE_CBFS_EXTERNAL_BINS) (NEW)
  3. Include external microcode header files (CPU_MICROCODE_CBFS_EXTERNAL_HEADER) (NEW)
  4. Do not include microcode updates (CPU_MICROCODE_CBFS_NONE) (NEW)
choice[1-4]: 1
*
* Northbridge
*
Use native raminit (USE_NATIVE_RAMINIT) [Y/n/?] (NEW) y
  Ignore vendor programmed fuses that limit max. DRAM frequency (NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES) [N/y/?] (NEW) y
  Ignore XMP profile max DIMMs per channel (NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS) [N/y/?] (NEW) y
Enable ECC if supported (RAMINIT_ENABLE_ECC) [Y/n/?] (NEW) y
*
* Southbridge
*
Validate Intel firmware descriptor (VALIDATE_INTEL_DESCRIPTOR) [N/y/?] (NEW) y
Lock down chipset in coreboot (INTEL_CHIPSET_LOCKDOWN) [Y/n/?] (NEW) n
*
* Super I/O
*
*
* Embedded Controllers
*
*
* Intel Firmware
*
Add Intel descriptor.bin file (HAVE_IFD_BIN) [Y/?] (NEW) y
  Path and filename of the descriptor.bin file (IFD_BIN_PATH) [3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin] (NEW) 
  Add Intel ME/TXE firmware (HAVE_ME_BIN) [Y/?] (NEW) y
    Path to management engine firmware (ME_BIN_PATH) [3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin] (NEW) /home/data/terminal/coreboot/coreboot/3rdparty/blobs/mainboard/sony/vpccb17fg/2.me.bin
    Verify the integrity of the supplied ME/TXE firmware (CHECK_ME) [N/y/?] (NEW) n
    Strip down the Intel ME/TXE firmware (USE_ME_CLEANER) [N/y/?] (NEW) y
      *
      * Please test the modified ME/TXE firmware and coreboot in two steps
      *
Protect flash regions
  1. Use the preset values to protect the regions (DO_NOT_TOUCH_DESCRIPTOR_REGION) (NEW)
  2. Lock ME/TXE section (LOCK_MANAGEMENT_ENGINE) (NEW)
> 3. Unlock flash regions (UNLOCK_FLASH_REGIONS) (NEW)
choice[1-3?]: 3
Bootblock behaviour
> 1. Always load fallback (BOOTBLOCK_SIMPLE) (NEW)
  2. Switch to normal if CMOS says so (BOOTBLOCK_NORMAL) (NEW)
choice[1-2]: 1
*
* Devices
*
Graphics initialization
> 1. Run VGA Option ROMs (VGA_ROM_RUN) (NEW)
  2. None (NO_GFX_INIT) (NEW)
choice[1-2]: 1
Use onboard VGA as primary video device (ONBOARD_VGA_IS_PRIMARY) [N/y/?] (NEW) n
Re-run VGA Option ROMs on S3 resume (S3_VGA_ROM_RUN) [Y/n/?] (NEW) y
Load Option ROMs on PCI devices (ON_DEVICE_ROM_LOAD) [N/y/?] (NEW) y
Option ROM execution type
> 1. Native mode (PCI_OPTION_ROM_RUN_REALMODE) (NEW)
  2. Secure mode (PCI_OPTION_ROM_RUN_YABEL) (NEW)
choice[1-2]: 1
*
* Display
*
Set framebuffer graphics resolution (FRAMEBUFFER_SET_VESA_MODE) [N/y/?] (NEW) y
  framebuffer graphics resolution
    1. 640x400 256-color (FRAMEBUFFER_VESA_MODE_100) (NEW)
    2. 640x480 256-color (FRAMEBUFFER_VESA_MODE_101) (NEW)
    3. 800x600 16-color (FRAMEBUFFER_VESA_MODE_102) (NEW)
    4. 800x600 256-color (FRAMEBUFFER_VESA_MODE_103) (NEW)
    5. 1024x768 16-color (FRAMEBUFFER_VESA_MODE_104) (NEW)
    6. 1024x768 256-color (FRAMEBUFFER_VESA_MODE_105) (NEW)
    7. 1280x1024 16-color (FRAMEBUFFER_VESA_MODE_106) (NEW)
    8. 1280x1024 256-color (FRAMEBUFFER_VESA_MODE_107) (NEW)
    9. 80x60 text (FRAMEBUFFER_VESA_MODE_108) (NEW)
    10. 132x25 text (FRAMEBUFFER_VESA_MODE_109) (NEW)
    11. 132x43 text (FRAMEBUFFER_VESA_MODE_10A) (NEW)
    12. 132x50 text (FRAMEBUFFER_VESA_MODE_10B) (NEW)
    13. 132x60 text (FRAMEBUFFER_VESA_MODE_10C) (NEW)
    14. 320x200 32k-color (1:5:5:5) (FRAMEBUFFER_VESA_MODE_10D) (NEW)
    15. 320x200 64k-color (5:6:5) (FRAMEBUFFER_VESA_MODE_10E) (NEW)
    16. 320x200 16.8M-color (8:8:8) (FRAMEBUFFER_VESA_MODE_10F) (NEW)
    17. 640x480 32k-color (1:5:5:5) (FRAMEBUFFER_VESA_MODE_110) (NEW)
    18. 640x480 64k-color (5:6:5) (FRAMEBUFFER_VESA_MODE_111) (NEW)
    19. 640x480 16.8M-color (8:8:8) (FRAMEBUFFER_VESA_MODE_112) (NEW)
    20. 800x600 32k-color (1:5:5:5) (FRAMEBUFFER_VESA_MODE_113) (NEW)
    21. 800x600 64k-color (5:6:5) (FRAMEBUFFER_VESA_MODE_114) (NEW)
    22. 800x600 16.8M-color (8:8:8) (FRAMEBUFFER_VESA_MODE_115) (NEW)
    23. 1024x768 32k-color (1:5:5:5) (FRAMEBUFFER_VESA_MODE_116) (NEW)
    24. 1024x768 64k-color (5:6:5) (FRAMEBUFFER_VESA_MODE_117) (NEW)
  > 25. 1024x768 16.8M-color (8:8:8) (FRAMEBUFFER_VESA_MODE_118) (NEW)
    26. 1280x1024 32k-color (1:5:5:5) (FRAMEBUFFER_VESA_MODE_119) (NEW)
    27. 1280x1024 64k-color (5:6:5) (FRAMEBUFFER_VESA_MODE_11A) (NEW)
    28. 1280x1024 16.8M-color (8:8:8) (FRAMEBUFFER_VESA_MODE_11B) (NEW)
    29. Manually select VESA mode (FRAMEBUFFER_VESA_MODE_USER) (NEW)
  choice[1-29?]: 29
  VESA mode (FRAMEBUFFER_VESA_MODE) [0x118] (NEW) 1920x1080
  VESA mode (FRAMEBUFFER_VESA_MODE) [0x118] (NEW)      
Framebuffer mode
> 1. Legacy VGA text mode (VGA_TEXT_FRAMEBUFFER) (NEW)
  2. VESA framebuffer (VBE_LINEAR_FRAMEBUFFER) (NEW)
choice[1-2]: 2
Show graphical bootsplash (BOOTSPLASH) [N/y/?] (NEW) y
Enable PCIe Common Clock (PCIEXP_COMMON_CLOCK) [Y/?] (NEW) y
Enable PCIe ASPM (PCIEXP_ASPM) [Y/?] (NEW) y
Enable PCIe Clock Power Management (PCIEXP_CLK_PM) [N/y/?] (NEW) y
Enable PCIe ASPM L1 SubState (PCIEXP_L1_SUB_STATE) [N/y/?] (NEW) y
Enable PCIe Hotplug Support (PCIEXP_HOTPLUG) [N/y/?] (NEW) y
  PCI Express Hotplug Buses (PCIEXP_HOTPLUG_BUSES) [32] (NEW) 64
  PCI Express Hotplug Memory (PCIEXP_HOTPLUG_MEM) [0x800000] (NEW) 
  PCI Express Hotplug Prefetch Memory (PCIEXP_HOTPLUG_PREFETCH_MEM) [0x10000000] (NEW) 
  PCI Express Hotplug Prefetch Memory Allocation below 4G boundary (PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G) [N/y/?] (NEW) ?

CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G:

This enables prefetch memory allocation below 4G boundary for the
hotplug resources.

Symbol: PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G [=n]
Type  : boolean
Prompt: PCI Express Hotplug Prefetch Memory Allocation below 4G boundary
  Location:
    -> Devices
      -> Enable PCIe Hotplug Support (PCIEXP_HOTPLUG [=y])
  Defined at src/device/Kconfig:598
  Depends on: PCIEXP_PLUGIN_SUPPORT [=y] && PCIEXP_HOTPLUG [=y]



  PCI Express Hotplug Prefetch Memory Allocation below 4G boundary (PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G) [N/y/?] (NEW) y
  PCI Express Hotplug I/O Space (PCIEXP_HOTPLUG_IO) [0x2000] (NEW) 
Early PCI bridge (EARLY_PCI_BRIDGE) [N/y/?] (NEW) y
  bridge device (EARLY_PCI_BRIDGE_DEVICE) [0x0] (NEW) 
  bridge function (EARLY_PCI_BRIDGE_FUNCTION) [0x0] (NEW) 
  MMIO window base (EARLY_PCI_MMIO_BASE) [0x0] (NEW) 
Override PCI Subsystem Vendor ID (SUBSYSTEM_VENDOR_ID) [0x0000] (NEW) 
Override PCI Subsystem Device ID (SUBSYSTEM_DEVICE_ID) [0x0000] (NEW) 
Add a VGA BIOS image (VGA_BIOS) [N/y/?] (NEW) n
Add a Video BIOS Table (VBT) binary to CBFS (INTEL_GMA_ADD_VBT) [N/y/?] (NEW) n
Enable I2C controller emulation in software (SOFTWARE_I2C) [N/y/?] (NEW) y
*
* Generic Drivers
*
Support for flash based event log (ELOG) [N/y/?] (NEW) y
  Enable debug output for event logging (ELOG_DEBUG) [N/y] (NEW) y
  Store a copy of ELOG in CBMEM (ELOG_CBMEM) [N/y/?] (NEW) y
  SMI interface to write and clear event log (ELOG_GSMI) [N/y/?] (NEW) y
  Maintain a monotonic boot number in CMOS (ELOG_BOOT_COUNT) [N/y/?] (NEW) y
Enable protection on MRC settings (MRC_SETTINGS_PROTECT) [N/y] (NEW) y
Support for flash based, SMM mediated data store (SMMSTORE) [N/y] (NEW) y
size of the SMMSTORE FMAP region (SMMSTORE_SIZE) [0x40000] (NEW) 
Disable Fast Read command (SPI_FLASH_NO_FAST_READ) [N/y/?] (NEW) n
Serial port on SuperIO (DRIVERS_UART_8250IO) [Y/n] (NEW) y
Oxford OXPCIe952 (DRIVERS_UART_OXPCIE) [N/y/?] (NEW) y
UART's PCI bus, device, function address (UART_PCI_ADDR) [0x0] (NEW) 
USB 2.0 EHCI debug dongle support (USBDEBUG) [N/y/?] (NEW) y
  Enable early (pre-RAM) usbdebug (USBDEBUG_IN_PRE_RAM) [Y/n/?] (NEW) y
  Index for EHCI controller to use with usbdebug (USBDEBUG_HCD_INDEX) [0] (NEW) y
  Index for EHCI controller to use with usbdebug (USBDEBUG_HCD_INDEX) [0] (NEW) 
  Default USB port to use as Debug Port (USBDEBUG_DEFAULT_PORT) [0] (NEW) 
  Type of dongle
  > 1. USB gadget driver or Net20DC (USBDEBUG_DONGLE_STD) (NEW)
    2. BeagleBone (not BeagleBone Black) (USBDEBUG_DONGLE_BEAGLEBONE) (NEW)
    3. FTDI FT232H UART (USBDEBUG_DONGLE_FTDI_FT232H) (NEW)
  choice[1-3]: 1
Support for Vital Product Data tables (VPD) [N/y/?] (NEW) y
Serial number in CBFS (DRIVERS_GENERIC_CBFS_SERIAL) [N/y/?] (NEW) y
Support runtime generation of Intel DPTF ACPI tables (DRIVERS_INTEL_DPTF) [N/y/?] (NEW) y
  If selected, use 'old' 7 character EISA IDs for DPTF _HID (DPTF_USE_EISA_HID) [N/y/?] (NEW) y
Support Intel PCI-e WiFi adapters (DRIVERS_INTEL_WIFI) [Y/n/?] (NEW) y
PS/2 keyboard init (DRIVERS_PS2_KEYBOARD) [N/y/?] (NEW) n
Silicon Image SIL3114 (DRIVERS_SIL_3114) [N/y/?] (NEW) y
*
* Security
*
*
* Verified Boot (vboot)
*
Verify firmware with vboot. (VBOOT) [N/y/?] (NEW) n
*
* Trusted Platform Module
*
Trusted Platform Module
> 1. disabled (USER_NO_TPM) (NEW)
choice[1]: 1
*
* Memory initialization
*
Always clear all DRAM on regular boot (SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT) [N/y/?] (NEW) y
Enable STM (STM) [N/y/?] (NEW) ?

CONFIG_STM:

Enabling the STM will load a simple hypervisor into SMM that will
restrict the actions of the SMI handler, which is the part of BIOS
that functions in system management mode (SMM).  The kernel can
configure the STM to prevent the SMI handler from accessing platform
resources.
The STM closes a vulnerability in Intel TXT (D-RTM)
The SMI handler provides a list of platform resources that it
requires access to the STM during STM startup, which the kernel
cannot override.
An additional capability, called STM-PE, provides a protected
execution capability that allows modules to be executed without
observation and interference. Examples of usage include kernel
introspection and virtualized trusted platform module (vTPM).
Requirement: SMM must be enabled and there must be sufficient room
within the TSEG to fit the MSEG.

Symbol: STM [=n]
Type  : boolean
Prompt: Enable STM
  Location:
    -> Security
  Defined at src/security/intel/stm/Kconfig:1
  Depends on: ENABLE_VMX [=y] && SMM_TSEG [=y]



Enable STM (STM) [N/y/?] (NEW) y
  *
  * SMI Transfer Monitor (STM)
  *
  mseg size (MSEG_SIZE) [0x400000] (NEW) 
  bios_resource_list_size (BIOS_RESOURCE_LIST_SIZE) [0x1000] (NEW) 
  STM binary file (STM_BINARY_FILE) [3rdparty/blobs/cpu/intel/stm/stm.bin] (NEW) 
Boot media protection mechanism
> 1. Don't lock boot media sections (BOOTMEDIA_LOCK_NONE) (NEW)
  2. Lock boot media using the controller (BOOTMEDIA_LOCK_CONTROLLER) (NEW)
  3. Lock boot media using the chip (BOOTMEDIA_LOCK_CHIP) (NEW)
choice[1-3]: 1
*
* Console
*
Enable early (bootblock) console output. (BOOTBLOCK_CONSOLE) [Y/n/?] (NEW) y
Enable console output during postcar. (POSTCAR_CONSOLE) [Y/n/?] (NEW) y
Squelch AP CPUs from early console. (SQUELCH_EARLY_SMP) [Y/n/?] (NEW) y
Serial port console output (CONSOLE_SERIAL) [Y/n/?] (NEW) y
*
* I/O mapped, 8250-compatible
*
*
* memory mapped, 8250-compatible
*
Index for UART port to use for console (UART_FOR_CONSOLE) [0] (NEW) 
*
* Serial port base address = 0x3f8
*
Baud rate
  1. 921600 (CONSOLE_SERIAL_921600) (NEW)
  2. 460800 (CONSOLE_SERIAL_460800) (NEW)
  3. 230400 (CONSOLE_SERIAL_230400) (NEW)
> 4. 115200 (CONSOLE_SERIAL_115200) (NEW)
  5. 57600 (CONSOLE_SERIAL_57600) (NEW)
  6. 38400 (CONSOLE_SERIAL_38400) (NEW)
  7. 19200 (CONSOLE_SERIAL_19200) (NEW)
  8. 9600 (CONSOLE_SERIAL_9600) (NEW)
choice[1-8]: 
spkmodem (console on speaker) console output (SPKMODEM) [N/y/?] (NEW) n
USB dongle console output (CONSOLE_USB) [Y/n/?] (NEW) y
Network console over NE2000 compatible Ethernet adapter (CONSOLE_NE2K) [N/y/?] (NEW) y
  Destination MAC address of remote system (CONSOLE_NE2K_DST_MAC) [00:13:d4:76:a2:ac] (NEW) 
  Destination IP of logging system (CONSOLE_NE2K_DST_IP) [10.0.1.27] (NEW) 
  IP address of coreboot system (CONSOLE_NE2K_SRC_IP) [10.0.1.253] (NEW) 
  NE2000 adapter fixed IO port address (CONSOLE_NE2K_IO_PORT) [0xe00] (NEW) 
Send console output to a CBMEM buffer (CONSOLE_CBMEM) [Y/n/?] (NEW) n
SPI Flash console output (CONSOLE_SPI_FLASH) [N/y/?] (NEW) y
  Room allocated for console output in FMAP (CONSOLE_SPI_FLASH_BUFFER_SIZE) [0x20000] (NEW) 
Default console log level
  1. 8: SPEW (DEFAULT_CONSOLE_LOGLEVEL_8) (NEW)
> 2. 7: DEBUG (DEFAULT_CONSOLE_LOGLEVEL_7) (NEW)
  3. 6: INFO (DEFAULT_CONSOLE_LOGLEVEL_6) (NEW)
  4. 5: NOTICE (DEFAULT_CONSOLE_LOGLEVEL_5) (NEW)
  5. 4: WARNING (DEFAULT_CONSOLE_LOGLEVEL_4) (NEW)
  6. 3: ERR (DEFAULT_CONSOLE_LOGLEVEL_3) (NEW)
  7. 2: CRIT (DEFAULT_CONSOLE_LOGLEVEL_2) (NEW)
  8. 1: ALERT (DEFAULT_CONSOLE_LOGLEVEL_1) (NEW)
  9. 0: EMERG (DEFAULT_CONSOLE_LOGLEVEL_0) (NEW)
choice[1-9]: 5
Don't show any POST codes (NO_POST) [N/y] (NEW) y
*
* System tables
*
Generate SMBIOS tables (GENERATE_SMBIOS_TABLES) [Y/n/?] (NEW) y
SMBIOS Serial Number (MAINBOARD_SERIAL_NUMBER) [123456789] (NEW) 593271650
SMBIOS Version Number (MAINBOARD_VERSION) [1.0] (NEW) 4.12
SMBIOS Manufacturer (MAINBOARD_SMBIOS_MANUFACTURER) [Sony] (NEW) 
SMBIOS Product name (MAINBOARD_SMBIOS_PRODUCT_NAME) [EMERALD LAKE 2] (NEW) VPCCB17FG
Populates SMBIOS type 0 version from the VPD_RO variable 'firmware_version' (VPD_SMBIOS_VERSION) [N/y/?] (NEW) y
*
* Payload
*
Add a payload
  1. None (PAYLOAD_NONE) (NEW)
  2. An ELF executable payload (PAYLOAD_ELF) (NEW)
  3. FILO (PAYLOAD_FILO) (NEW)
  4. GRUB2 (PAYLOAD_GRUB2) (NEW)
  5. LinuxBoot (PAYLOAD_LINUXBOOT) (NEW)
> 6. SeaBIOS (PAYLOAD_SEABIOS) (NEW)
  7. U-Boot (Experimental) (PAYLOAD_UBOOT) (NEW)
  8. Yabits - Yet another UEFI Bootloader (Under Development) (PAYLOAD_YABITS) (NEW)
  9. A Linux payload (PAYLOAD_LINUX) (NEW)
  10. Tianocore payload (PAYLOAD_TIANOCORE) (NEW)
choice[1-10]: 8
Yabits version
> 1. Stable (YABITS_STABLE) (NEW)
  2. Master (YABITS_MASTER) (NEW)
  3. git revision (YABITS_REVISION) (NEW)
choice[1-3]: 2
Add a PXE ROM (PXE) [N/y] (NEW) y
  *
  * PXE Options
  *
  PXE ROM to use
  > 1. Add an existing PXE ROM image (PXE_ROM) (NEW)
    2. Build and add an iPXE ROM (BUILD_IPXE) (NEW)
  choice[1-2]: 2
  iPXE version
  > 1. 2019.3 (IPXE_STABLE) (NEW)
    2. master (IPXE_MASTER) (NEW)
  choice[1-2]: 1
  network card PCI IDs (PXE_ROM_ID) [10ec,8168] (NEW) 
  Enable iPXE serial console (PXE_SERIAL_CONSOLE) [Y/n/?] (NEW) y
  Do not show prompt to boot from PXE (PXE_NO_PROMPT) [N/y/?] (NEW) y
  Embed an iPXE script for automated provisioning (PXE_ADD_SCRIPT) [N/y/?] (NEW) n
  Enable HTTPS protocol (PXE_HAS_HTTPS) [Y/n/?] (NEW) y
Payload compression algorithm
  1. Use no compression for payloads (COMPRESSED_PAYLOAD_NONE) (NEW)
> 2. Use LZMA compression for payloads (COMPRESSED_PAYLOAD_LZMA) (NEW)
  3. Use LZ4 compression for payloads (COMPRESSED_PAYLOAD_LZ4) (NEW)
choice[1-3?]: 2
Use LZMA compression for secondary payloads (COMPRESS_SECONDARY_PAYLOAD) [Y/n/?] (NEW) y
*
* Secondary Payloads
*
Load coreinfo as a secondary payload (COREINFO_SECONDARY_PAYLOAD) [N/y/?] (NEW) y
Load Memtest86+ as a secondary payload (MEMTEST_SECONDARY_PAYLOAD) [N/y/?] (NEW) y
Load nvramcui as a secondary payload (NVRAMCUI_SECONDARY_PAYLOAD) [N/y/?] (NEW) y
Load tint as a secondary payload (TINT_SECONDARY_PAYLOAD) [N/y/?] (NEW) y
Memtest86+ version
> 1. Stable (MEMTEST_STABLE) (NEW)
  2. Master (MEMTEST_MASTER) (NEW)
  3. git revision (MEMTEST_REVISION) (NEW)
choice[1-3]: 2
*
* Debugging
*
*
* CPU Debug Settings
*
*
* BLOB Debug Settings
*
*
* General Debug Settings
*
GDB debugging support (GDB_STUB) [N/y/?] (NEW) y
  Wait for a GDB connection in the ramstage (GDB_WAIT) [N/y/?] (NEW) n
Halt when hitting a BUG() or assertion error (FATAL_ASSERTS) [N/y/?] (NEW) y
Output verbose CBFS debug messages (DEBUG_CBFS) [N/y/?] (NEW) n
Output verbose RAM init debug messages (DEBUG_RAM_SETUP) [N/y/?] (NEW) n
Output verbose SMBus debug messages (DEBUG_SMBUS) [N/y/?] (NEW) n
Output verbose SMI debug messages (DEBUG_SMI) [N/y/?] (NEW) n
Debug console initialisation code (DEBUG_CONSOLE_INIT) [N/y/?] (NEW) y
Output verbose SPI flash debug messages (DEBUG_SPI_FLASH) [N/y/?] (NEW) n
Trace function calls (TRACE) [N/y/?] (NEW) y
Debug code coverage (DEBUG_COVERAGE) [N/y/?] (NEW) y
Debug boot state machine (DEBUG_BOOT_STATE) [N/y/?] (NEW) y
Compile debug code in Ada sources (DEBUG_ADA_CODE) [N/y/?] (NEW) y
Platform can support the Dediprog EM100 SPI emulator (HAVE_EM100_SUPPORT) [Y/?] (NEW) y
  Configure image for EM100 usage (EM100) [N/y/?] (NEW) y
*
* Restart config...
*
*
* General setup
*
Local version string (LOCALVERSION) [4.12] 4.12
Compiler to use
> 1. GCC (COMPILER_GCC)
  2. LLVM/clang (TESTING ONLY - Not currently working) (COMPILER_LLVM_CLANG)
choice[1-2?]: 1
Allow building with any toolchain (ANY_TOOLCHAIN) [Y/n/?] y
Use ccache to speed up (re)compilation (CCACHE) [Y/n/?] y
Generate flashmap descriptor parser using flex and bison (FMD_GENPARSER) [Y/n/?] y
Generate SCONFIG & BINCFG parser using flex and bison (UTIL_GENPARSER) [Y/n/?] y
Use CMOS for configuration values (USE_OPTION_TABLE) [Y/?] y
  Load default configuration values into CMOS on each boot (STATIC_OPTION_TABLE) [Y/n/?] y
Compress ramstage with LZMA (COMPRESS_RAMSTAGE) [Y/n/?] y
Include the coreboot .config file into the ROM image (INCLUDE_CONFIG_FILE) [Y/n/?] y
Create a table of timestamps collected during boot (COLLECT_TIMESTAMPS) [N/y/?] n
Allow use of binary-only repository (USE_BLOBS) [Y/n/?] y
  Allow AMD blobs repository (with license agreement) (USE_AMD_BLOBS) [N/y/?] n
  Allow QC blobs repository (selecting this agrees to the license!) (USE_QC_BLOBS) [Y/n/?] y
Code coverage support (COVERAGE) [Y/n/?] y
Undefined behavior sanitizer support (UBSAN) [Y/n/?] y
Stage Cache for ACPI S3 resume
  1. Disabled (NO_STAGE_CACHE)
> 2. TSEG (TSEG_STAGE_CACHE) (NEW)
choice[1-2]: 2
Update existing coreboot.rom image (UPDATE_IMAGE) [Y/n/?] y
Add a bootsplash image (BOOTSPLASH_IMAGE) [Y/n/?] y
  Bootsplash path and filename (BOOTSPLASH_FILE) [/home/data/lib/Pictures/lelouch.zero.beast.png] /home/data/lib/Pictures/lelouch.zero.beast.png
Firmware Configuration Probing (FW_CONFIG) [Y/n/?] y
  Obtain Firmware Configuration value from CBFS (FW_CONFIG_SOURCE_CBFS) [Y/n/?] y
#
# configuration written to /home/data/terminal/coreboot/coreboot/.config
#
hd-scania:[hd_scania]:/home/data/terminal/coreboot/coreboot$

Last edited by hd_scania; 07-13-2020 at 06:41 AM.
 
Old 07-13-2020, 06:03 AM   #2
hd_scania
Member
 
Registered: Apr 2017
Location: Tuen-mun, Hong Kong, Great Britain
Distribution: Plenties found in my signatures :)
Posts: 208

Original Poster
Blog Entries: 4

Rep: Reputation: Disabled
Code:
hd-scania:[hd_scania]:/home/data/terminal/coreboot/coreboot$ sudo smbios-sys-info && sudo smbios-sys-info-lite
Libsmbios version:      2.4.3
Product Name:           VPCCB17FG
Vendor:                 Sony Corporation
BIOS Version:           R0242V2
System ID:              Could not determine System ID.
Service Tag:            27538883-7000615
Express Service Code:   0
Asset Tag:              N/A
Property Ownership Tag: 
Libsmbios:    2.4.3
Error getting the System ID:    unknown error.
Service Tag:  27538883-7000615
Express Service Code: 172273558179
Asset Tag:  N/A
Product Name: VPCCB17FG
BIOS Version: R0242V2
Vendor:       Sony Corporation
Is Dell:      0
OEM String 1: 1034672416H
OEM String 2: FNC-EXTB
OEM String 3: A3FM35fUNkXWM5fUw61WMbxgw61QGtpXnOcj1QNkXWO5fUwkXW
OEM String 4: Reserved
OEM String 5: 7.0.4.1197
hd-scania:[hd_scania]:/home/data/terminal/coreboot/coreboot$
Code:
File vpccb17fg.legacy.bios.rom is 4194304 bytes
  Flash Region 0 (Flash Descriptor): 00000000 - 00000fff 
  Flash Region 1 (BIOS): 00000000 - 00000fff 
  Flash Region 2 (Intel ME): 00000000 - 00000fff 
  Flash Region 3 (GbE): 00000000 - 00000fff 
  Flash Region 4 (Platform Data): 00000000 - 00000fff
Code:
Found chipset "Intel HM65".
FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only.
FREG2: Management Engine region (0x00001000-0x001fffff) is locked.
Not all flash regions are freely accessible by flashrom. This is most likely
due to an active ME.
 
Old 07-14-2020, 08:28 AM   #3
hd_scania
Member
 
Registered: Apr 2017
Location: Tuen-mun, Hong Kong, Great Britain
Distribution: Plenties found in my signatures :)
Posts: 208

Original Poster
Blog Entries: 4

Rep: Reputation: Disabled
Code:
hd_scania@hd-scania:/home/data/terminal/coreboot/coreboot$ make
    GEN        generated/assembly.inc
    CC         romstage/arch/x86/assembly_entry.o
    GEN        build.h
    CC         romstage/lib/version.o
    LINK       cbfs/fallback/romstage.debug
/home/data/terminal/coreboot/coreboot/util/crossgcc/xgcc/bin/x86_64-elf-ld.bfd:build/romstage/drivers/elog/boot_count.o: file format not recognized; treating as linker script
/home/data/terminal/coreboot/coreboot/util/crossgcc/xgcc/bin/x86_64-elf-ld.bfd:build/romstage/drivers/elog/boot_count.o:1: syntax error
make: *** [src/arch/x86/Makefile.inc:185: build/cbfs/fallback/romstage.debug] Error 1
hd_scania@hd-scania:/home/data/terminal/coreboot/coreboot$ cat cbfs/fallback/romstage.debug
cat: cbfs/fallback/romstage.debug: No such file or directory
hd_scania@hd-scania:/home/data/terminal/coreboot/coreboot$ cat build/romstage/drivers/elog/boot_count.o
build/romstage/drivers/elog/boot_count.o: src/drivers/elog/boot_count.c \
 src/include/kconfig.h build/config.h src/include/rules.h \
 src/commonlib/bsd/include/commonlib/bsd/compiler.h \
 src/include/console/console.h src/include/stdint.h \
 src/arch/x86/include/arch/cpu.h src/include/types.h \
 src/commonlib/bsd/include/commonlib/bsd/cb_err.h src/include/stdbool.h \
 src/include/stddef.h src/commonlib/include/commonlib/helpers.h \
 src/commonlib/bsd/include/commonlib/bsd/helpers.h \
 src/commonlib/bsd/include/commonlib/bsd/compiler.h \
 src/include/console/post_codes.h src/include/console/vtxprintf.h \
 src/include/stdarg.h src/commonlib/include/commonlib/loglevel.h \
 src/include/ip_checksum.h src/include/pc80/mc146818rtc.h \
 src/arch/x86/include/arch/io.h src/include/elog.h build/option_table.h
hd_scania@hd-scania:/home/data/terminal/coreboot/coreboot$ rm build/romstage/drivers/elog/boot_count.o
removed 'build/romstage/drivers/elog/boot_count.o'
hd_scania@hd-scania:/home/data/terminal/coreboot/coreboot$ make
    GEN        generated/assembly.inc
    CC         romstage/arch/x86/assembly_entry.o
    CC         romstage/drivers/elog/boot_count.o
src/drivers/elog/boot_count.c: In function 'boot_count_cmos_read':
src/drivers/elog/boot_count.c:17:34: error: 'CMOS_VSTART_boot_count_offset' undeclared (first use in this function); did you mean 'CMOS_VSTART_reboot_counter'?
 # define BOOT_COUNT_CMOS_OFFSET (CMOS_VSTART_boot_count_offset >> 3)
                                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
src/drivers/elog/boot_count.c:41:18: note: in expansion of macro 'BOOT_COUNT_CMOS_OFFSET'
   *p = cmos_read(BOOT_COUNT_CMOS_OFFSET + i);
                  ^~~~~~~~~~~~~~~~~~~~~~
src/drivers/elog/boot_count.c:17:34: note: each undeclared identifier is reported only once for each function it appears in
 # define BOOT_COUNT_CMOS_OFFSET (CMOS_VSTART_boot_count_offset >> 3)
                                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
src/drivers/elog/boot_count.c:41:18: note: in expansion of macro 'BOOT_COUNT_CMOS_OFFSET'
   *p = cmos_read(BOOT_COUNT_CMOS_OFFSET + i);
                  ^~~~~~~~~~~~~~~~~~~~~~
src/drivers/elog/boot_count.c: In function 'boot_count_cmos_write':
src/drivers/elog/boot_count.c:17:34: error: 'CMOS_VSTART_boot_count_offset' undeclared (first use in this function); did you mean 'CMOS_VSTART_reboot_counter'?
 # define BOOT_COUNT_CMOS_OFFSET (CMOS_VSTART_boot_count_offset >> 3)
                                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
src/drivers/elog/boot_count.c:70:18: note: in expansion of macro 'BOOT_COUNT_CMOS_OFFSET'
   cmos_write(*p, BOOT_COUNT_CMOS_OFFSET + i);
                  ^~~~~~~~~~~~~~~~~~~~~~
src/drivers/elog/boot_count.c: At top level:
cc1: error: unrecognized command line option '-Wno-address-of-packed-member' [-Werror]
cc1: all warnings being treated as errors
make: *** [Makefile:362: build/romstage/drivers/elog/boot_count.o] Error 1
hd_scania@hd-scania:/home/data/terminal/coreboot/coreboot$ touch build/romstage/drivers/elog/boot_count.o && make
    GEN        generated/assembly.inc
    CC         romstage/arch/x86/assembly_entry.o
    GEN        build.h
    CC         romstage/lib/version.o
    LINK       cbfs/fallback/romstage.debug
/home/data/terminal/coreboot/coreboot/util/crossgcc/xgcc/bin/x86_64-elf-ld.bfd: build/romstage/drivers/elog/boot_count.o: file not recognized: file truncated
make: *** [src/arch/x86/Makefile.inc:185: build/cbfs/fallback/romstage.debug] Error 1
hd_scania@hd-scania:/home/data/terminal/coreboot/coreboot$

Last edited by hd_scania; 07-14-2020 at 08:30 AM.
 
Old 07-15-2020, 01:38 AM   #4
hd_scania
Member
 
Registered: Apr 2017
Location: Tuen-mun, Hong Kong, Great Britain
Distribution: Plenties found in my signatures :)
Posts: 208

Original Poster
Blog Entries: 4

Rep: Reputation: Disabled
Code:
hd_scania@hd-scania:~$ sudo dmidecode -t bios -t baseboard
# dmidecode 3.2
Getting SMBIOS data from sysfs.
SMBIOS 2.6 present.
Handle 0x0000, DMI type 0, 24 bytes
BIOS Information
        Vendor: American Megatrends Inc.
        Version: R0242V2
        Release Date: 09/22/2011
        Address: 0xF0000
        Runtime Size: 64 kB
        ROM Size: 4096 kB
        Characteristics:
                PCI is supported
                PNP is supported
                BIOS is upgradeable
                BIOS shadowing is allowed
                ESCD support is available
                Boot from CD is supported
                Selectable boot is supported
                EDD is supported
                8042 keyboard services are supported (int 9h)
                CGA/mono video services are supported (int 10h)
                ACPI is supported
                USB legacy is supported
                AGP is supported
                Smart battery is supported
                BIOS boot specification is supported
                Function key-initiated network boot is supported
                Targeted content distribution is supported
        BIOS Revision: 2.42
        Firmware Revision: 2.42
Handle 0x0002, DMI type 2, 10 bytes
Base Board Information
        Manufacturer: Sony Corporation
        Product Name: VAIO
        Version: N/A
        Serial Number: N/A
        Asset Tag: N/A
        Features:
                Board is a hosting board
hd_scania@hd-scania:~$
 
  


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