https://slashdot.org/story/21/05/14/...dry-in-arizona

This, to my mind, is a lot more like it. The timescales seem to make sense, too. Up to 5 years for 3nm, and then as much time or more for 2nm.

The guys already have 5nm (= the best there currently is), they have engineers at the forefront of this tech, and clearly see a way to get 3nm, whether it's doping tweaks, FET redesign, less voltage or whatever. Personally, I'm surprised by Arizona. It's much nearer an earthquake fault than I would like.

Back in the 1990s(?) Intel built it's FAB14 factory in Newbridge, Co. Kildare in Ireland which is nowhere near an earthquake fault line. The first fAB line IIRC, was 64nm.They had a truly miserable pass rate, and traced the faults to miniature seismological disturbances. So they solved it by digging a deep trench all around the factory, and isolating it from the vibrations. So you have to cross a bridge to get into Intel's Newbridge factory. Maybe it's the local roads, or the not so local earthquakes. Doing that got their pass rate (for fabricated chips) up to 2%, which they boasted about in the business.

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never heard about that, thanks for sharing
i never would have thought that it would be a problem.

I just heard about it because my brother knew someone from his engineering class working on the job. He's a Mechanical Engineer.

Mind you, TMSC might be about to find out the hard way

Here's an interesting link from Slashdot on CPU core errors
https://hardware.slashdot.org/story/...re-modern-cpus

which inclines me to think that the problem I mentioned earlier of stray electrons penetrating increasingly thin insulation may already be out in the wild. Crucially, what this article doesn't reveal is:

• The CPUs involved.
• The lithography of fab size.
• The manufacturer.
• The range of core voltage.

There has been a lot of work on doping, but individual atomic mixes of doping material could even have been patented. Additionally, in the normal situation, part of the 'N' doped and part of the 'P' doped neutralises. So you don't get a "++++++------" junction, but rather "++++NNNN----". The width of the 'NNNN' bit is depending on the bias applied, which is determined in part by core voltage. As you forward bias a junction, the 'NNNN' bit is eroded and vanishes as the junction is switched on. So a core may work at 0.8V but throw the odd error at 1.2V, or vice versa. I'm not well enough into chip fabrication to be sure. One thing is sure: any gates not pulled to 0V will throw errors. There is inclined to be less doubt about Drain & Source voltages, but in the middle of an IC, who can tell?

In any case, the size requirement is so small, there's not enough room for the 'NNNN' bit. So the doping endeavours to thin it as much as possible, and that's how errors come through. It makes you wonder about these 250W and 280W CPU packages with fantastic core counts.The smallest FAB we have ATM is 5nm - Apple's M1 & M2; AMD goes to 7nm, unless I missed news recently. And Intel is hanging out on 10nm, last heard, although plans for smaller are progressing.

In short, this makes me think that IBM's 2nm wafer fab is fantasy, or creative accounting.

But I gather from the text that we're talking about server cpus with presumably 20+ cores which could be severely heat cycled over their lifetimes.

EDIT: I'm not in the least surprised that testing fails to pick this up.Validating the function of an electronic component at ambient is basically impossible.

I am attaching a link, but first I feel obliged to give a heavy technobabble warning
https://semiwiki.com/semiconductor-s...ly-a-2nm-node/

According to the semiconductor wiki, in reality it's a 3nm node (2.9nm to be precise) and compared with TMSC & Samsung plans it doesn't seem that great. That said - Let's face it, any 3nm node that turns out product is great.

What's also interesting is that many of the process parts are at minimum already. Wire is an example. It fuses on low diameter. We talk about wafer width and 3 dimensions, but wafer width can be profiled for power or performance.