Summarizing from bits of information I gathered from here and there, i found that atomics are supported and added as one of the ECN to pci-sig.

Now I am trying to display the graphics cards atomic support by lspci s <pci_address> -vv command. Someone else is able to get atomic status displayed from verbose output (-vv) of lspci (1) but in my case, I just could not after trynig several servers(2)

(1)

DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR-

... EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS-
AtomicOpsCap: 32bit+ 64bit+ 128bitCAS-

(2)
DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-


How do I cause the lspci to display? I am using ubuntu1804 with linux kernel 5.4.xx.
Do I have build the kernel with specific options?
Thanks.,

I would like links for your 'here and there.'

It is available in pci-sig but for members only.

PCI-SIG ENGINEERING CHANGE NOTICE
TITLE: Atomic Operations

Part I
1. Summary of the Functional Changes
This optional normative ECN defines 3 new PCIe transactions, each of which carries out a specific
Atomic Operation (“AtomicOp”) on a target location in Memory Space. The 3 AtomicOps are FetchAdd
(Fetch and Add), Swap (Unconditional Swap), and CAS (Compare and Swap). FetchAdd and Swap
support operand sizes of 32 and 64 bits. CAS supports operand sizes of 32, 64, and 128 bits.
Endpoints and Root Ports may serve as Requesters for AtomicOps. PCIe Functions with Memory Space
BARs as well as all Root Ports may serve as Completers for AtomicOp Requests. Routing elements
(Switches, as well as Root Complexes supporting peer-to-peer access between Root Ports) require
modification in order to route AtomicOp Requests. AtomicOps are architected for device-to-host, deviceto-device, and host-to-device transactions.
Four new bits in the Device Capabilities 2 register enable software to discover specific AtomicOp
Completer capabilities in arbitrary PCIe Functions, and AtomicOp routing capability in routing elements.
Software discovery of AtomicOp Requester capabilities is not architected, but a new AtomicOp Requester
Enable bit in the Device Control 2 register must be set by software in order for a Function to initiate
AtomicOp Requests. Software can set a new AtomicOp Egress Blocking bit in routing element Ports as
needed to avoid forwarding (“block”) AtomicOp Requests to components that shouldn’t receive them.