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Trouble with kernel DHT11 driver on Orange PI
Hello! Can anybody please help me?
I'm using armbian on Orange PI 3B v2.1, chip RK3566 and have troubles reading value from DHT11 Kernel: Linux orangepi3b 6.1.115-vendor-rk35xx Sensor driver: kernel driver drivers/iio/humidity/dht11.c I'm attaching DHT11 to GPIO3_D0 pin, and create node in DTB. But when trying to read value from it, I get errors (after enabling debug): Code:
[ 2504.491143] dht11 dht11@0: current timeresolution: 41nsHave anybody encountered same trouble with gpio edges detection? |
GPIO Troubleshooting Suggestions
There are many things that can affect how accurately edges are detected by software. Some are hardware related, and some depend on how software configures the GPIO hardware.
I usually check these kinds of things.
If you are not getting closer to solving a problem, change something and observe the effect. Try to verify individual assumptions using other hardware or software. Re-read documentation or find other sources of documentation to see if they agree. Problems can be frustrating but they are also how we get experience and learn things. |
Hi Erik!
Thank you for response! 1. voltage level correct - 3.3 volts. Communication speed about 10 kHz, and datasheet doesn't specify termination resistors 2. edges looks pretty good. Problem is not in too much false edges, but otherwise, orange pi doesn't detect some of edges - should be 83 edges detected (42*2-1) 3. I've tested dht11 with arduino, there it works absolutely ok 4. I use built-in vanilla kernel driver for dht11, no extra software 5. driver always explicitly configures gpio to detect both edges - rising and falling 6. yes, I will try to reproduce edge detection troubles with other source 7. changing rate is impossible, dht11 uses it's own encoding method for sending data: 25 us peak for transmitting 0, 70 us peak for transmitting 1 8. driver uses interrupts for detecting edges, so I'm trying to understand how set interrupt priority 9. I tried on arduino and stm32, but I'll try on RPi too 10. I use linux 6.1.15, driver's logic didn't modified since then, but it looks that problem not in driver itself, but in edge detecions |
From Post #1:
Hello Vlad. I'm a hardware guy and there's only one way to find out what's going on. Beg/borrow or hire an oscilloscope. History lesson: In the beginning, logic was TTL, and specified * V≤0.8V Guaranteed Logic Low # V@0.8-2.0V Intermediate, Undetermined. In fact, as you descended from 2.0V the Voltage stayed High but usually switched either side of 1.0-1.2V, but not cleanly. * Voltage≥2.0V Guaranteed Logic Level High. Electronically, that was the stone age. In practise now for 3.3V circuitry, below about0.7V is low, above a volt is high, but you don't want to see thresholds. You want clean levels away from thresholds. This is why you need the oscilloscope. Stick a clip on ground, poke the gpio pins and let them run - don't synch or trigger the trace, As the low levels and high levels run past, check the levels. This sort of thing comes from low levels that are not actually low or high levels that are not high, or high enough. |
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But may be slow raising edge matters, it has no spikes or ringing, just slow
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How High are the LOW levels? That's the critical point. It's when your low levels are interpeted as high that things go crazy. Change your 'scope to 0.2V/cm and check again. Oscilloscopes are tolerant of overload. It might just be a few pins - that's why the free running trace is best.
Just FYI, modern cpus (AMD for sure) can run with cpu core VDD (= + Volts, literally 'Drain Voltages') as low as 0.8V. With a PN junction, nothing gets through without 0.5V bias. I'd expect a FET gate to need more, but probably between 0.55-0.8V everything happens, low, intermediate, high. This is at the cpu core. The voltages go up further out, but the speeds go down. I did a project with 74HCAUC Logic, which handled 250MHz but it ran on 2.5V. Of interest is the wafer fab size? Can you find the spec? And where are you measuring the voltages? GPIO Pins would probably be safest. |
How High are the LOW levels? That's the critical point. It's when your low levels are interpeted as high that things go crazy. Change your 'scope to 0.2V/cm and check again. Oscilloscopes are tolerant of overload. It might just be a few pins - that's why the free running trace is best.
Just FYI, modern cpus (AMD for sure) can run with cpu core VDD (= + Volts, literally 'Drain Voltages') as low as 0.8V. With a PN junction, nothing gets through without 0.5V bias. I'd expect a FET gate to need more, but probably between 0.55-0.8V everything happens, low, intermediate, high. This is at the cpu core. The voltages go up further out, but the speeds go down. I did a project with 74HCAUC Logic, which handled 250MHz but it ran on 2.5V. Of interest is the wafer fab size? Can you find the spec? And where are you measuring the voltages? GPIO Pins would probably be safest. I looked at your trace. That's good. There's 10-15pF in the gate input capacitance, (externally) and a resistive looking pull-up. It could be a mosfet or resistor. I don't know the impedance, so I'll guess 10k for the example. Now there's a techie's approximation for the time to raise 2/3 VDD. Just multiply R x C, in this case 10^3 = 1^4x 12^-12 = 1.2^-7 or 0.12µS. But that's to get 2/3 way up your waveform, (=2.2V)whereas the switching would have taken place ≤1.5V, so you only need to get up to about halfway on the curve to guarantee switching in worst case scenarios. I would: Connect the probe to earth, and adjust your trace vertically to be exactly on a horizontal line.Set to 0.2V/cm, don't trigger, and let it run free. You should see clear lows or highs, but a faulty component may cause intermediate levels. Finding that is another matter(!), but knowing it's faulty allows you to replace.I would set zero on the bottom but one line, so you could see -0.2V if it came. It shouldn't! You should see 1 volt or more onscreen. Check your low levels & report back. |
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Right. Your hardware gets a clean bill of health, the rise time is to be expected. The top speed of the logic comes when the rise time isn't finished before the negative edge, if you follow me. But your hardware looks fine.
I worked in Industrial Electronics, and never met GPIO. Industrial Electronics used discrete ICs, but the modern cpu is most unsuited to the task of switching GPIO pins. Make sure the GPIO pins will operate on 3.3V. They might need 5V pull-ups, if the cpu is 5V tolerant. But usually it's a software issue. After my experience in the 1980s, I made a note to self never to use/repair GPIO. I've seen folks go grey over the duration of a project. There is help online, software, etc. Use it. There are also microcontrollers, which are ideal for driving GPIO. You have 8 (or 16 bit) ports. They also have I²C serial ports, and an adress/data bus. You can issue a port instruction to set the GPIO legs. But I'd read, try support forums, give all relevant information (unlike here!) and take the advice. EDIT: You'll find Raspberry Pi much better documented than Orange Pi. Good guides - even on gpio. EDIT_2: You're always better off using level detection than edge detection with GPIO. GPIO is not timing sensitive. Each switching needs it's own song & dance routine. |
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