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Old 03-22-2020, 01:46 PM   #1
zvivered
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Time from interrupt signal to user space handling


Hello,

Under vanilla 4.9.20 (x32, busybox) I'm running the following application:

An FPGA creates a PCIe (MSIx) interrupt every 2msec.
The interrupt is handled by a kernel driver.
Upon creating the interrupt, timetag(T1) is locked in a 32 bits register in FPGA.

The application launches a thread.
This thread sends an IOCTL request to the device driver.
This IOCTL is answered upon interrupt.
At this point, timetag(T2) is read.

I loogged T2-T1 and expected it to be less than 100usec.
But this diff is sometimes ~500msec.

The kernel is built with CONFIG_PREEMPT (Low-Latency Desktop)
Is it wise to set the priority of my process to the highest possible value ?

Thank you,
Zvika
 
Old 03-24-2020, 08:45 AM   #2
TB0ne
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Location: Birmingham, Alabama
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Quote:
Originally Posted by zvivered View Post
Hello,
Under vanilla 4.9.20 (x32, busybox) I'm running the following application:

An FPGA creates a PCIe (MSIx) interrupt every 2msec. The interrupt is handled by a kernel driver. Upon creating the interrupt, timetag(T1) is locked in a 32 bits register in FPGA.

The application launches a thread. This thread sends an IOCTL request to the device driver. This IOCTL is answered upon interrupt. At this point, timetag(T2) is read. I loogged T2-T1 and expected it to be less than 100usec. But this diff is sometimes ~500msec.

The kernel is built with CONFIG_PREEMPT (Low-Latency Desktop) Is it wise to set the priority of my process to the highest possible value ?
Since you again:
  • Don't post your code
  • Tell us anything about the 'application'
  • Tell us what your goal is
  • Tell us anything about what you've done/tried to solve your problem
What do you think we can tell you? Based on your numerous threads over quite some time, you have created a custom embedded system and wrote a driver for it...only YOU are going to possess the knowledge needed to determine what is 'wise' to do, to meet your goals. Are you actually having a *PROBLEM* with things? Is something not working??? System crashing???? Anything???
 
Old 03-26-2020, 03:01 PM   #3
zvivered
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Registered: Sep 2007
Posts: 294

Original Poster
Rep: Reputation: 23
Hello,

The problem is the long (~500usec) delay between the interrupt signal to start handling it in the application.
This is unacceptable in our embedded system.

The application contains 2 threads:

int InterruptThread (void *pParam)
{
while (1)
{
//Block till interrupt
Diff = CurrentTimetag - InterrptTimetag; //InterrptTimetag is read from FPGA
if (MaxDiff > Diff)
MaxDiff = Diff;

}
}

int main (void)
{
// Initialized FPGA

//Create Thread

while (1)
{
sleep (1);
}
}

Is there a way to make this delay shorter ?

Thank you,
Zvika

Last edited by zvivered; 03-26-2020 at 03:15 PM.
 
Old 03-26-2020, 03:11 PM   #4
TB0ne
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Quote:
Originally Posted by zvivered View Post
Hello,
The problem is the long (~500usec) delay between the interrupt signal to start handling it in the application. This is unacceptable in our embedded system. The application contains 2 threads:
Code:
int main (void)
{
   // Initialized FPGA

   //Create Thread 
}
Ok, so AGAIN:
  • You post NO CODE
  • You provide NO DETAILS
What do you think we'll be able to tell you or suggest??? If it's 'unacceptable' for you, then *CHANGE YOUR CODE* You STILL don't say what the actual problem is, aside from it being somehow unacceptable. You have the custom code..you have the custom platform, and at this point only YOU know what its doing...no one here does.

So what do you want us to tell you?
 
Old 04-03-2020, 03:57 PM   #5
business_kid
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+1 on TBone's comment. We don't actually care, but we can't fix what we can't see.

In addition, you're thinking of your fpga as a cpu, I feel. It's like a cpu in ways but it's s set of gates pretending to be a cpu; That can be executed efficiently or very inefficiently depending on your vhdl, and your chip. You don't give us clock speeds, cpu cycles, n o t h i n g. So I would suggest work it out, or let us see the problem.
 
  


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