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Old 11-01-2020, 06:18 AM   #1
ayyasprings
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how does memory layout placing done with uboot image in a dead board?


Hi,

In LD Script of U boot we can specify the memory layout of object files of specific sections of uboot source code to be aligned in executable.

But I have a basic doubt how does that information in that executable gets interpreted by any JTAG like debugger to place that uboot image in fresh board that was not at all brought up until that time.

I understand that it varies from board to board, soc to soc, or processor to processor, but what will be the basic general idea?

Please reply.
 
Old 11-01-2020, 10:01 AM   #2
business_kid
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Uboot is software. Jtag began as lower level - basically a hardware tester for PCB Assembly line. It only returns pass/fail. What it has metamorphosed into in the last 15 years is another matter.

The idea behind jtag was that jtag pins, clock & signal ran to all jtag-capable ICs. As clock signals go through a pcb, one chip after another reports the high or low level of each pin on the device. The code is compared with a good board. If a chip is missing, r a 'high' is shorted low, jtag will detect it. The board then goes to techies, or is junked, depending on price.

EDIT: JTAG connections are serial, iirc, so that you see 1 chip at a time. As you keep clocking, the digital state of each pin in order (which is the output) forms the output to the tester.

Last edited by business_kid; 11-01-2020 at 11:54 AM.
 
Old 11-02-2020, 05:55 AM   #3
ayyasprings
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hi business_kid,

I think you did not understand my doubt.

I will rephrase that here.

In a fresh board which has no software in it, how do the j tag like debugger places/positions - the U boot like bootloader image software - in the expected memory layout - which was already specified in the bootloader image by LD Script at the time of building the bootloader image?

please reply.
 
Old 11-02-2020, 12:53 PM   #4
business_kid
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Besides all the functioning parts of a circuit, JTAG lines are connected serially. JTAG has
  1. Clock in
  2. Clock out
  3. Data in
  4. Data out
on some plug. the way the board is designed, specifically the order in which chips are connected, determines the output. If you're the board designer or manufacturer, you know this stuff. If you're not, you don't need to know this stuff and they won't tell you.

In the particular case you mention, more or less memory, JTAG 'in' lines will be bridged to JTAG 'out' lines in place of missing chips. The code will be different and that code will be used for that memory config. Now, forget JTAG. You can't use it.

Last edited by business_kid; 11-02-2020 at 12:55 PM.
 
  


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