It should work easily man ...
There's no other complex ideas here.
I gone through this back. But with write I had problem at first time.
There will be read & write enable pins in NVRAM (active low), which get low when reading/writing and this signals will be sent from processor via the lines connected to pins READ/WRITE Enable.
In my case these bits were not configured (kept inactive) in that approprite chip select mapped to NVRAM. Later, I set those flags to activate READ?WRITE bits.
This was the only effort, I had to go through..., to bring up my NVRAM device.
NVRAM is same as RAM with NON-VOLATILE functionality... It doesn't require any special actions as we do it for FLASH. Only needy things are write/read enable bits and I assume the data bus always works perfect...