[SOLVED] GCC Optimization and make.conf?

drillsar · 05-05-2019, 01:43 PM

I determined my cpu is ivybridge with 4 cores with one thread

in /mnt/gentoo/etc/portage/make.conf

Code:

CHOST="x86_64-pc-linux-gnu"
CFLAGS="-march=ivybridge -O2 -pipe"
CXXFLAGS="${CFLAGS}"
MAKEOPTS="-j4"

is this correct?

rylan76 · 05-16-2019, 08:39 AM

AFAIK whether that works will depend on the GCC version you have installed.

E. g. I checked my GCC on Centos 7 and it is version

Quote:

# gcc --version
gcc (GCC) 4.8.5 20150623 (Red Hat 4.8.5-36)

and according to its local man page, it does NOT support an architecture string "ivybridge" in the

-march

commandline parameter.

(E. g. you probably need a newer GCC than 4.8.5 20150623 - and if you have one, check in its man pages if supports "ivybridge" as a target machine architecture.)

From the 4.8.5 GCC manpage on my Centos 7 box:

Code:

Intel 386 and AMD x86-64 Options
These -m options are defined for the i386 and x86-64 family of computers:

-march=cpu-type
Generate instructions for the machine type cpu-type. In contrast to -mtune=cpu-type, which merely tunes the generated code
for the specified cpu-type, -march=cpu-type allows GCC to generate code that may not run at all on processors other than the
one indicated. Specifying -march=cpu-type implies -mtune=cpu-type.

The choices for cpu-type are:

native
This selects the CPU to generate code for at compilation time by determining the processor type of the compiling machine.
Using -march=native enables all instruction subsets supported by the local machine (hence the result might not run on
different machines). Using -mtune=native produces code optimized for the local machine under the constraints of the
selected instruction set.

i386
Original Intel i386 CPU.

i486
Intel i486 CPU. (No scheduling is implemented for this chip.)

i586
pentium
Intel Pentium CPU with no MMX support.

pentium-mmx
Intel Pentium MMX CPU, based on Pentium core with MMX instruction set support.

pentiumpro
Intel Pentium Pro CPU.

i686
When used with -march, the Pentium Pro instruction set is used, so the code runs on all i686 family chips. When used with
-mtune, it has the same meaning as generic.

pentium2
Intel Pentium II CPU, based on Pentium Pro core with MMX instruction set support.

pentium3
pentium3m
Intel Pentium III CPU, based on Pentium Pro core with MMX and SSE instruction set support.
pentium-m
Intel Pentium M; low-power version of Intel Pentium III CPU with MMX, SSE and SSE2 instruction set support. Used by
Centrino notebooks.

pentium4
pentium4m
Intel Pentium 4 CPU with MMX, SSE and SSE2 instruction set support.

prescott
Improved version of Intel Pentium 4 CPU with MMX, SSE, SSE2 and SSE3 instruction set support.

nocona
Improved version of Intel Pentium 4 CPU with 64-bit extensions, MMX, SSE, SSE2 and SSE3 instruction set support.

core2
Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support.

corei7
Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 instruction set support.

corei7-avx
Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AES and PCLMUL instruction set
support.

core-avx-i
Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AES, PCLMUL, FSGSBASE, RDRND and
F16C instruction set support.

core-avx2
Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AES, PCLMUL,
FSGSBASE, RDRND, FMA, BMI, BMI2 and F16C instruction set support.

atom
Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support.

k6 AMD K6 CPU with MMX instruction set support.

k6-2
k6-3
Improved versions of AMD K6 CPU with MMX and 3DNow! instruction set support.

athlon
athlon-tbird
AMD Athlon CPU with MMX, 3dNOW!, enhanced 3DNow! and SSE prefetch instructions support.

athlon-4
athlon-xp
athlon-mp
Improved AMD Athlon CPU with MMX, 3DNow!, enhanced 3DNow! and full SSE instruction set support.

k8
opteron
athlon64
athlon-fx
Processors based on the AMD K8 core with x86-64 instruction set support, including the AMD Opteron, Athlon 64, and Athlon
64 FX processors. (This supersets MMX, SSE, SSE2, 3DNow!, enhanced 3DNow! and 64-bit instruction set extensions.)

k8-sse3
opteron-sse3
athlon64-sse3
Improved versions of AMD K8 cores with SSE3 instruction set support.

amdfam10
barcelona
CPUs based on AMD Family 10h cores with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSE4A,
3DNow!, enhanced 3DNow!, ABM and 64-bit instruction set extensions.)

bdver1
CPUs based on AMD Family 15h cores with x86-64 instruction set support. (This supersets FMA4, AVX, XOP, LWP, AES,
PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)

bdver2
AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP,
AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)

bdver3
AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP,
AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.

btver1
CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSSE3,
SSE4A, CX16, ABM and 64-bit instruction set extensions.)

btver2
CPUs based on AMD Family 16h cores with x86-64 instruction set support. This includes MOVBE, F16C, BMI, AVX, PCL_MUL, AES,
SSE4.2, SSE4.1, CX16, ABM, SSE4A, SSSE3, SSE3, SSE2, SSE, MMX and 64-bit instruction set extensions.

winchip-c6
IDT WinChip C6 CPU, dealt in same way as i486 with additional MMX instruction set support.

winchip2
IDT WinChip 2 CPU, dealt in same way as i486 with additional MMX and 3DNow! instruction set support.

c3 VIA C3 CPU with MMX and 3DNow! instruction set support. (No scheduling is implemented for this chip.)

c3-2
VIA C3-2 (Nehemiah/C5XL) CPU with MMX and SSE instruction set support. (No scheduling is implemented for this chip.)

geode
AMD Geode embedded processor with MMX and 3DNow! instruction set support.

E. g. no "ivybridge".

Regards

Stefan

sevendogsbsd · 05-16-2019, 08:52 AM

When I ran Gentoo, I don't ever remember specifically naming a CPU in my make.conf, plus I thought the "-j" flag was number of cores +1. Is that not the case any more?

drillsar · 05-17-2019, 06:37 AM

I went here and as you can see they have -march=ivybridge

https://wiki.gentoo.org/wiki/Safe_CFLAGS#Ivy_Bridge

sevendogsbsd · 05-17-2019, 12:06 PM

Are you using distcc? If not, the recommended way to set up make.conf is "A recommended default choice for CFLAGS or CXXFLAGS is to use -march=native. This enables auto-detection of the CPU's architecture."

Code:

CFLAGS="-O2 -pipe -march=native"
CXXFLAGS="${CFLAGS}"

If you ARE using distcc, there is documentation on how to set up these flags in make.conf.